240pin DDR3 SDRAM Unbuffered DIMMs
Preliminary
DDR3 SDRAM Unbuffered DIMMs
Based on 1Gb A ver.
HMT164U6AFP6C
HMT112U6AFP8C
HMT112U7AFP8C
HMT125U6AFP8C
HMT125U7AFP8C
** Since DDR3 Specification has not been defined completely yet
in JEDEC, this document may contain items under discussion.
** Contents may be changed at any time without any notice.
Rev. 0.01 / Nov 2007
1
HMT164U6AFP6C
HMT112U6(7)AFP8C
HMT125U6(7)AFP8C
Revision History
Revision No.
0.01
History
Initial draft for internal review
Draft Date
2007-11
Remark
Rev. 0.01 / Nov 2007
2
HMT164U6AFP6C
HMT112U6(7)AFP8C
HMT125U6(7)AFP8C
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Speed Grade & Key Parameters
1.3 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 512MB, 64Mx64 Module(1Rank of x16)
3.2 1GB, 128Mx64 Module(1Rank of x8)
3.3 1GB, 128Mx72 ECC Module(1Rank of x8)
3.4 2GB, 256Mx64 Module(2Rank of x8)
3.5 2GB, 256Mx72 ECC Module(2Rank of x8)
4. Address Mirroring Feature
4.1 DRAM Pin Wiring for Mirroring
5. Absolute Maximum Ratings
5.1 Absolute Maximum DC Ratings
5.2 Operating Temperature Range
6. AC & DC Operating Conditions
6.1 Recommended DC Operating Conditions
6.2 DC & AC Logic Input Levels
6.2.1 For Single-ended Signals
6.2.2 For Differential Signals
6.2.3 Differential Input Cross Point
6.3 Slew Rate Definition
6.3.1 For Ended Input Signals
6.3.2 For Differential Input Signals
6.4 DC & AC Output Buffer Levels
6.4.1 Single Ended DC & AC Output Levels
6.4.2 Differential DC & AC Output Levels
6.4.3 Single Ended Output Slew Rate
6.4.4 Differential Ended Output Slew Rate
6.5 Overshoot/Undershoot Specification
6.6 Input/Output Capacitance & AC Parametrics
6.7 IDD Specifications & Measurement Condtiions
7. Electrical Characteristics and AC Timing
7.1 Refresh Parameters by Device Density
7.2 DDR3 Standard speed bins and AC para
8. DIMM Outline Diagram
8.1 512MB, 64Mx64 Module(1Rankx16)
8.2 1GB, 128Mx64 Module(1Rank of x8)
8.3 1GB, 128Mx72 ECC Module(1Rank of x8)
8.4 2GB, 256Mx64 Module(2Rank of x8)
8.5 2GB, 256Mx72 ECC Module(2Rank of x8)
Rev. 0.01 / Nov 2007
3
HMT164U6AFP6C
HMT112U6(7)AFP8C
HMT125U6(7)AFP8C
1. Description
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine
Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 1Gb
A ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitble for
easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V
• VDDSPD=3.3V to 3.6V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with
CK transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• Programmable additive latency 0, CL-1, and CL-2 sup
ported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package : JEDEC standard 82ball
FBGA(x4/x8) , 100ball FBGA(x16) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• On Die Thermal Sensor supported ( JEDEC optional )
• 8 bit pre-fetch
1.1.2 Ordering Information
# of
# of
Materials
DRAMs ranks
4
8
9
16
18
1
1
1
2
2
Lead free
Lead free
Lead free
Lead free
Lead free
Part Name
HMT164U6AFP6C-S6/S5/G8/G7/H9/H8*N0
HMT112U6AFP8C-S6/S5/G8/G7/H9/H8N0
HMT112U7AFP8C-S6/S5/G8/G7/H9/H8T0
HMT125U6AFP8C-S6/S5/G8/G7/H9/H8N0
HMT125U7AFP8C-S6/S5/G8/G7/H9/H8T0
Density
512MB
1GB
1GB
2GB
2GB
Org
64Mx64
128Mx64
128Mx72
256Mx64
256Mx72
ECC
None
None
ECC
None
ECC
TS
None
None
Support
None
Support
* For more details of option code, please contact local Hynix Sales Representatives!
Rev. 0.01 / Nov 2007
4
HMT164U6AFP6C
HMT112U6(7)AFP8C
HMT125U6(7)AFP8C
1.2 Speed Grade & Key Parameters
MT/S
Grade
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
CL-tRCD-tRP
6
15
15
37.5
52.5
6-6-6
DDR3-800
-S6
2.5
5
12.5
12.5
37.5
50
5-5-5
8
15
15
37.5
52.5
8-8-8
-S5
DDR3-1066
-G8
1.875
7
13.125
13.125
37.5
50.625
7-7-7
9
13.5
13.5
36
49.5
9-9-9
-G7
DDR3-1333
-H9
1.5
8
12
12
36
48
8-8-8
10
12.5
12.5
35
47.25
10-10-10
-H8
DDR3-1600
Unit
-P1
1.25
9
11.25
11.25
35
46.25
9-9-9
-P9
ns
tCK
ns
ns
ns
ns
tCK
1.3 Address Table
512MB
Organization
Refresh Method
Row Address
Column Address
Bank Address
Page Size
# of Rank
# of Device
64M x 64
8K/64ms
A0-A12
A0-A9
BA0-BA2
2KB
1
4
1GB
128M x 64
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
1
8
1GB
128M x 72
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
1
9
2GB
256M x 64
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
2
16
2GB
256M x 72
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
2
18
Rev. 0.01 / Nov 2007
5
微控制器 MCU
