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HSMP-4820-TR2G

Pin Diode, 50V V(BR), Silicon, ROHS COMPLIANT, SOT-23, 3 PIN

器件类别:分立半导体    二极管   

厂商名称:Broadcom(博通)

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Broadcom(博通)
包装说明
R-PDSO-G3
Reach Compliance Code
compliant
ECCN代码
EAR99
其他特性
LOW DISTORTION
应用
LIMITER; SWITCHING
最小击穿电压
50 V
配置
SINGLE
最大二极管电容
1 pF
标称二极管电容
0.75 pF
二极管元件材料
SILICON
最大二极管正向电阻
0.6 Ω
二极管电阻测试电流
10 mA
二极管类型
PIN DIODE
频带
L BAND
JESD-30 代码
R-PDSO-G3
JESD-609代码
e4
湿度敏感等级
1
元件数量
1
端子数量
3
最高工作温度
150 °C
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度(摄氏度)
260
最大功率耗散
0.25 W
认证状态
Not Qualified
反向测试电压
20 V
表面贴装
YES
技术
POSITIVE-INTRINSIC-NEGATIVE
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式
GULL WING
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
Base Number Matches
1
文档预览
HSMP-382x, 482x
Surface Mount RF PIN Switch and Limiter Diodes
Data Sheet
Description/Applications
The HSMP-382x series is optimized for switching ap-
plications where ultra-low resistance is required. The
HSMP-482x diode is ideal for limiting and low induc-
tance switching applications up to 1.5 GHz.
A SPICE model is not available for PIN diodes as SPICE
does not provide for a key PIN diode characteristic, carrier
lifetime.
Features
Diodes Optimized for:
Low Current Switching
Low Distortion Attenuating
Power Limiting /Circuit Protection
Surface Mount SOT-23 and SOT-323 Packages
Single and Dual Versions
Tape and Reel Options Available
Low Failure in Time (FIT) Rate
[1]
Lead-free
Note:
1. For more information see the Surface Mount PIN Reliability
Data Sheet.
Package Lead Code Identification, SOT-23 (Top View)
SINGLE
SERIES
Package Lead Code Identification, SOT-323 (Top View)
DUAL ANODE
#0
COMMON
ANODE
#2
COMMON
CATHODE
HSMP-482B
#3
DUAL ANODE
#4
HSMP-4820
Absolute Maximum Ratings
[1]
T
C
= +25°C
Symbol
I
f
P
IV
T
j
T
stg
θ
jc
Parameter
Forward Current (1 μs Pulse)
Peak Inverse Voltage
Junction Temperature
Storage Temperature
Thermal Resistance
[2]
Unit
Amp
V
°C
°C
°C/W
SOT-23
1
50
150
-65 to 150
500
SOT-323
1
50
150
-65 to 150
150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the
device.
2. T
C
= +25°C, where T
C
is defined to be the temperature at the package pins where contact is
made to the circuit board.
Electrical Specifications T
C
= 25°C
Part Number
HSMP-
3820
3822
3823
3824
Test Conditions
Package
Marking
Code
F0
F2
F3
F4
Lead
Code
0
2
3
4
Configuration
Single
Series
Common Anode
Common Cathode
Minimum
Breakdown
Voltage V
BR
(V)
50
Maximum
Series Resistance
R
S
(Ω)
0.6
Maximum
Total Capacitance
C
T
(pF)
0.8
V
R
= V
BR
Measure
I
R
≤ 10 μA
f = 100 MHz
I
F
= 10 mA
f = 1 MHz
V
R
= 20 V
High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes
Part
Number
HSMP-
4820
482B
Package
Marking
Code
FA
FA
Lead
Code
A
A
Minimum
Breakdown
Voltage
V
BR
(V)
50
V
R
= V
BR
Measure
I
R
≤ 10 μA
Maximum
Series
Resistance
R
S
(Ω)
0.6
I
F
= 10 mA
Typical
Total
Capacitance
C
T
(pF)
0.75
f = 1 MHz
V
R
= 20 V
Maximum
Total
Capacitance
C
T
(pF)
1.2
f = 1 MHz
V
R
= 0 V
Typical
Total
Inductance
L
T
(nH)
1.0
f = 500 MHz –
3 GHz
Configuration
Dual Anode
Dual Anode
Test Conditions
Typical Parameters at T
C
= 25°C
Part Number
HSMP-
382x
Test Conditions
Series Resistance
R
S
(Ω)
1.5
f = 100 MHz
I
F
= 10 mA
Carrier Lifetime
τ (ns)
70
I
F
= 10 mA
Reverse Recovery Time
T
rr
(ns)
7
V
R
= 10 V
I
F
= 20 mA
90% Recovery
Total Capacitance
C
T
(pF)
0.60 @ 20 V
2
Typical Parameters at T
C
= 25°C (unless otherwise noted), Single Diode
T
rr
– REVERSE RECOVERY TIME (ns)
100
100
100
I
F
– FORWARD CURRENT (mA)
10
V
R
= 2V
V
R
= 5V
10
V
R
= 10V
RF RESISTANCE (OHMS)
30
10
1
1
0.1
–50C
0.8
1.0
1.2
125C
0.01
0
0.2
0.4
25C
0.6
1
10
20
FORWARD CURRENT (mA)
V
F
– FORWARD VOLTAGE (mA)
0.1
0.01
0.1
1
10
100
I
F
– FORWARD BIAS CURRENT (mA)
Figure 1. Forward Current vs. Forward Voltage.
Figure 2. Reverse Recovery Time vs. Forward
Current for Various Reverse Voltages.
Figure 3. RF Resistance at 25C vs. Forward Bias
Current.
1.4
120
INPUT INTERCEPT POINT (dBm)
1.2
CW POWER OUT (dBm)
CAPACITANCE (pF)
Diode Mounted as a
Series Attenuator in a
115
50 Ohm Microstrip and
Tested at 123 MHz
110
105
100
95
90
85
30
25
20
15
10
5
0
Measured with external
bias return
0
5
10
15
20
25
30
35
40
1.5 GHz
1.0
1.0 GHz
0.8
0.6
0
10
20
30
40
50
1
10
30
V
R
– REVERSE VOLTAGE (V)
I
F
– FORWARD BIAS CURRENT (mA)
CW POWER IN (dBm)
Figure 4. Capacitance vs. Reverse Voltage.
Figure 5. 2nd Harmonic Input Intercept Point vs.
Forward Bias Current.
Figure 6. Large Signal Transfer Curve of the
HSMP-482x Limiter.
Typical Applications for Multiple Diode Products
RF COMMON
RF COMMON
RF 1
RF 2
RF 1
RF 2
BIAS 1
BIAS 2
BIAS
BIAS
Figure 7. Simple SPDT Switch, Using Only Positive Current.
Figure 8. High Isolation SPDT Switch, Dual Bias.
3
Typical Applications for Multiple Diode Products,
continued
RF COMMON
BIAS
RF COMMON
RF 1
RF 2
RF 1
BIAS
RF 2
Figure 9. Switch Using Both Positive and Negative Bias Current.
Figure 10. Very High Isolation SPDT Switch, Dual Bias.
BIAS
Figure 11. High Isolation SPST Switch (Repeat Cells as Required.
Figure 12. Power Limiter Using HSMP-3822 Diode Pair.
See Application Note 1050 for details.
4
Typical Applications for HSMP-482x Low Inductance
Series
Microstrip Series Connection for HSMP-482x Series
In order to take full advantage of the low inductance
of the HSMP-482x series when using them in series
applications, both lead 1 and lead 2 should be connected
together, as shown in Figure 14.
3
1.5 nH
1.5 nH
0.8 pF
0.3 nH
0.3 nH
Figure 16. Equivalent Circuit.
1
2
Co-Planar Waveguide Shunt Connection for HSMP-482x Series
Co-Planar waveguide, with ground on the top side of
the printed circuit board, is shown in Figure 17. Since
it eliminates the need for via holes to ground, it offers
lower shunt parasitic inductance and higher maximum
attenuation when compared to a microstrip circuit. See
AN1050 for details.
Co-Planar Waveguide
Groundplane
Center Conductor
Groundplane
Figure 13. Internal Connections.
Figure 14. Circuit Layout.
Microstrip Shunt Connections for HSMP-482x Series
In Figure 15, the center conductor of the microstrip line
is interrupted and leads 1 and 2 of the HSMP-482x diode
are placed across the resulting gap. This forces the 0.5
nH lead inductance of leads 1 and 2 to appear as part of
a low pass filter, reducing the shunt parasitic inductance
and increasing the maximum available attenuation.
The 0.3 nH of shunt inductance external to the diode
is created by the via holes, and is a good estimate for
0.032" thick material.
50 OHM MICROSTRIP LINES
0.8 pF
Figure 17. Circuit Layout.
0.75 nH
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
Figure 18. Equivalent Circuit.
Figure 15. Circuit Layout, HSMP-482x Limiter.
5
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