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HUF75623P3, HUF75623S3ST
Data Sheet
December 2001
22A, 100V, 0.064 Ohm, N-Channel,
UltraFET® Power MOSFETs
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
JEDEC TO-263AB
DRAIN
(FLANGE)
Features
• Ultra Low On-Resistance
- r
DS(ON)
= 0.064Ω,
V
GS
=
10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
GATE
SOURCE
DRAIN
(FLANGE)
HUF75623P3
HUF75623S3ST
Symbol
D
Ordering Information
PART NUMBER
PACKAGE
TO-220AB
TO-263AB
BRAND
75623P
75623S
HUF75623P3
HUF75623S3ST
G
S
NOTE: When ordering, use the entire part number i.e., HUF75623P3
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
HUF75623P3, HUF75623S3ST
UNITS
V
V
V
A
A
100
100
±20
22
15
Figure 4
Figures 6, 14, 15
85
0.57
-55 to 175
300
260
W
W/
o
C
o
C
o
C
o
C
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
NOTE:
1. T
J
= 25
o
C to 150
o
C.
CAUTION:
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75623P3, HUF75623S3ST Rev. B
HUF75623P3, HUF75623S3ST
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
DSS
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
DS
= 95V, V
GS
= 0V
V
DS
= 90V, V
GS
= 0V, T
C
= 150
o
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to
Ambient
R
θJC
R
θJA
TO-220
-
-
-
-
1.76
62
o
C/W
o
C/W
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
-
-
-
-
-
-
-
-
1
250
±100
V
µA
µA
nA
I
GSS
V
GS
=
±20V
V
GS(TH)
r
DS(ON)
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
I
D
= 22A, V
GS
= 10V (Figure 9)
2
-
-
0.054
4
0.064
V
Ω
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
-
-
790
215
70
-
-
-
pF
pF
pF
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 50V,
I
D
= 22A,
I
g(REF)
= 1.0mA
(Figures 13, 16, 17)
-
-
-
-
-
43
23
1.7
3.5
8.7
52
28
2
-
-
nC
nC
nC
nC
nC
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
V
DD
= 50V, I
D
= 22A
V
GS
=
10V,
R
GS
= 13Ω
(Figures 18, 19)
-
-
-
-
-
-
-
7.9
42
47
39
-
75
-
-
-
-
130
ns
ns
ns
ns
ns
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
SYMBOL
V
SD
I
SD
= 22A
I
SD
= 11A
Reverse Recovery Time
Reverse Recovered Charge
t
rr
Q
RR
I
SD
= 22A, dI
SD
/dt = 100A/µs
I
SD
= 22A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.00
100
313
UNITS
V
V
ns
nC
©2001 Fairchild Semiconductor Corporation
HUF75623P3, HUF75623S3ST Rev. B
HUF75623P3, HUF75623S3ST
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
I
D
, DRAIN CURRENT (A)
20
V
GS
= 10V
15
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
25
10
5
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
Z
θJC
, NORMALIZED
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-3
10
-2
t, RECTANGULAR PULSE DURATION (s)
10
-1
10
0
10
1
SINGLE PULSE
0.01
10
-5
10
-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
300
T
C
= 25
o
C
I
DM
, PEAK CURRENT (A)
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
V
GS
= 10V
175 - T
C
150
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10
-5
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF75623P3, HUF75623S3ST Rev. B
HUF75623P3, HUF75623S3ST
Typical Performance Curves
300
I
AS
, AVALANCHE CURRENT (A)
SINGLE PULSE
T
J
= MAX RATED
T
C
= 25
o
C
(Continued)
100
I
D
, DRAIN CURRENT (A)
100
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
1ms
10ms
100
300
10
0.001
0.01
0.1
1
t
AV
, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
30
40
V
GS
= 20V
V
GS
= 10V
I
D
, DRAIN CURRENT (A)
30
V
GS
= 7V
V
GS
= 6V
I
D
, DRAIN CURRENT (A)
20
T
J
= 175
o
C
10
20
V
GS
= 5V
T
J
= -55
o
C
T
J
= 25
o
C
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
0
1
2
3
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
4
0
2
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
3
4
6
0
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
3.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
V
GS
= 10V, I
D
= 22A
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
V
GS
= V
DS
, I
D
= 250µA
2.0
1.5
1.0
0.5
0
-80
1.0
0.8
0.6
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF75623P3, HUF75623S3ST Rev. B
