HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
512Mb NAND FLASH
HY27US(08/16)12(1/2)B
HY27US0812(1/2)B
HY27US1612(1/2)B
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.5 / Jul. 2007
1
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
0.1
Initial Draft.
1) Correct Figure 14 & 15
1) Add AC Characteristics
0.2
- tRB : Last RE High to busy (at sequential read)
- tCRY : CE High to Ready (in case of interception by CE at read)
- tCEH : CE High Hold Time (at the last serial read)
0.3
1) Add sequential row read feature and figure
2) Modify Block Replacement
1) Add x16 Characteristics
0.4
2) Modify read2 operation (sequential row read)
3) Add AC Characteristics
- tOH : RE or CE High to Output Hold
1) Correct Read ID Table 16
0.5
2) Correct System Interface Using CE don’t care operation
3) Correct Command Set Table 5
Jul. 20. 2007
May. 29. 2007
Apr. 27. 2007
Mar. 26. 2007
History
Draft Date
Oct. 19. 2006
Mar. 07. 2007
Remark
Preliminary
Rev 0.5 / Jul. 2007
2
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code
SUPPLY VOLTAGE
- VCC = 2.7 to 3.6V : HY27US(08/16)12(1/2)B
Memory Cell Array
x8 : (512+16) Bytes x 32 Pages x 4,096 Blocks
x16 : (256+8) Words x 32 Pages x 4,096 Blocks
PAGE SIZE
- x8 device : (512+16) Bytes
: HY27US0812(1/2)B
- x16 device : (256+8) Words
: HY27US1612(1/2)B
DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27US(08/16)12(1/2)B-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27US(08/16)12(1/2)B-T (Lead)
- HY27US(08/16)12(1/2)B-TP (Lead Free)
- HY27US0812(1/2)B-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27US0812(1/2)B-S (Lead)
- HY27US0812(1/2)B-SP (Lead Free)
- HY27US0812(1/2)B-F(P)
: 63-Ball FBGA (9 x 11 x 1.0 mm)
- HY27US0812(1/2)B-F (Lead)
- HY27US0812(1/2)B-FP (Lead Free)
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
CE DON’t CARD OPTION ONLY
CHIP ENABLE DON’T CARE
- Simple interface with microcontroller
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
PAGE READ / PROGRAM
- Random access: 12us (max.)
- Sequential access: 30ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
Rev 0.5 / Jul. 2007
3
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The Hynix HY27US(08/16)12(1/2)B series is a 64Mx8bit with spare 2Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Their NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is
erased.
The memory contains 4096 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected Flash
cells.
A program operation allows to write the 512-byte (x8 device) or 256-word (x16 device) page in typical 200us and an erase
operation can be performed in typical 2ms on a 16K-byte (X8 device) block.
Data in the page can be read out at 30ns cycle time (3.3V device) per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards differ-
ent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modify operations can be locked using the WP input pin .
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple
memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27US(08/16)12(1/2)B extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip is offered with the CE don’t care function. This option allows the direct download of the code from the NAND Flash
memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails the
data can be directly programmed in another page inside the same array section without the time consuming serial data
insertion phase.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HY27US(08/16)12(1/2)B is available in 48 - TSOP1 12 x 20 mm package, 48 - USOP1 12 x 17 mm, FBGA 9 x 11 mm.
1.1 Product List
PART NUMBER
HY27US0812(1/2)B
HY27US1612(1/2)B
ORIZATION
x8
x16
VCC RANGE
2.7V - 3.6 Volt
PACKAGE
48TSOP1/ 48USOP1/ 63FBGA
48TSOP1
Rev 0.5 / Jul. 2007
4
HY27US(08/16)12(1/2)B Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Input / Outputs (x16 only)
Data Inputs / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1: Signal Names
Rev 0.5 / Jul. 2007
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