Title Page
IBM PowerPC 970FX RISC Microprocessor
Datasheet
Version 2.5
March 26, 2007
®
Copyright and Disclaimer
©
Copyright International Business Machines Corporation 2005, 2006, 2007
All Rights Reserved
Printed in the United States of America March 2007
The following are trademarks of International Business Machines Corporation in the United States, or other countries,
or both.
IBM
IBM Logo
ibm.com
PowerPC
PowerPC Architecture
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document
are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction
could result in death, bodily injury, or catastrophic property damage. Nothing in this document shall operate as an express
or implied license or indemnity under the intellectual property rights of IBM or third parties, or give rise to any express or
implied warranty. Information contained in this document was obtained in specific environments, and is presented as an
illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be
liable for damages arising directly or indirectly from any use of the information contained in this document.
IBM Systems and Technology Group
2070 Route 52, Bldg. 330
Hopewell Junction, NY 12533-6351
The IBM home page can be found at
ibm.com®
The IBM Semiconductor solutions home page can be found at
ibm.com/chips
March 26, 2007
Datasheet
PowerPC 970FX RISC Microprocessor
Contents
List of Figures ................................................................................................................. 5
List of Tables ................................................................................................................... 7
Revision Log ................................................................................................................... 9
About This Datasheet ................................................................................................... 11
1. General Information .................................................................................................. 13
1.1 Description ....................................................................................................................................
1.2 Features .........................................................................................................................................
1.3 PowerPC 970FX RISC Microprocessor Block Diagram .............................................................
1.4 Ordering and Processor Version Register .................................................................................
1.4.1 Standard Lead Package Version ...........................................................................................
1.4.2 Reduced-Lead Package Version ...........................................................................................
13
13
15
16
16
17
2. General Parameters .................................................................................................. 19
3. Electrical and Thermal Characteristics ................................................................... 21
3.1 dc Electrical Characteristics ........................................................................................................
3.1.1 Absolute Maximum Ratings ...................................................................................................
3.1.2 Recommended Operating Conditions ...................................................................................
3.1.3 Package Thermal Characteristics ..........................................................................................
3.1.4 dc Electrical Specifications ....................................................................................................
3.1.5 Power Consumption ..............................................................................................................
3.2 ac Electrical Characteristics ........................................................................................................
3.3 Clock ac Specifications ................................................................................................................
3.4 Processor-Clock Timing Relationship between PSYNC and SYSCLK ....................................
3.5 Processor Interconnect Specifications .......................................................................................
3.5.1 Electrical and Physical Specifications ...................................................................................
3.5.1.1 Source Synchronous Bus ...............................................................................................
3.5.1.2 Drive Side Characteristics ..............................................................................................
3.5.1.3 Module-to-Module Interconnect Characteristics .............................................................
3.5.1.4 Receive Side Characteristics .........................................................................................
3.6 Input ac Specifications .................................................................................................................
3.6.1 TBEN Input Pin ......................................................................................................................
3.7 Asynchronous Output Specifications .........................................................................................
3.8 Mode Select Input Timing Specifications ...................................................................................
3.9 Spread Spectrum Clock Generator .............................................................................................
3.9.1 Design Considerations ..........................................................................................................
3.10 I
2
C and JTAG ...............................................................................................................................
3.10.1 I
2
C Bus Timing Information .................................................................................................
3.10.2 IEEE 1149.1 ac Timing Specifications .................................................................................
3.10.3 I
2
C and JTAG Considerations .............................................................................................
3.10.4 Boundary Scan Considerations ...........................................................................................
Version 2.5
March 26, 2007
21
21
21
22
23
24
26
26
28
30
30
30
30
31
32
34
35
36
37
40
40
41
41
41
43
43
Contents
Page 3 of 78
Datasheet
PowerPC 970FX RISC Microprocessor
4. Dimensions and Physical Signal Assignments ...................................................... 45
4.1 Electrostatic Discharge Considerations .....................................................................................
4.2 Mechanical Packaging ..................................................................................................................
4.2.1 Standard Lead Package Version ...........................................................................................
4.2.2 Reduced-Lead Package Version ...........................................................................................
4.2.2.1 Mechanical Specifications ..............................................................................................
4.2.2.2 Assembly Considerations ...............................................................................................
4.3 PowerPC 970FX Microprocessor Pinout Listings ......................................................................
45
45
45
48
49
49
55
5. System Design Information ...................................................................................... 63
5.1 External Resistors .........................................................................................................................
5.2 Phase-Locked Loop Configuration ..............................................................................................
5.2.1 Determining PLLMULT and BUS_CFG Settings ...................................................................
5.2.2 PLL_RANGE Configuration ...................................................................................................
5.2.3 Typical PLL and SYSCLK Configurations ..............................................................................
5.3 PLL Power Supply Filtering ..........................................................................................................
5.4 Decoupling Recommendations ....................................................................................................
5.4.1 Using the KVPRBVDD and KVPRBGND Pins .......................................................................
5.5 Decoupling Layout Guide .............................................................................................................
5.6 Pullup and Pulldown Recommendations ....................................................................................
5.7 Input-Output Use ...........................................................................................................................
5.7.1 Chip Signal I/O and Test Pins ................................................................................................
5.8 Thermal Management Information ...............................................................................................
5.8.1 Thermal Management Pins ....................................................................................................
5.8.2 Reading Thermal Diode Calibration Data through JTAG .......................................................
5.8.3 Heatsink Attachment and Mounting Forces ...........................................................................
5.9 Operational and Design Considerations .....................................................................................
5.9.1 Power-On Reset Considerations ...........................................................................................
5.9.2 Debugging PowerPC 970FX Power-On and Reset Sequence ..............................................
5.9.3 I
2
C Addressing of PowerPC 970FX .......................................................................................
63
63
63
64
64
66
67
67
68
69
71
71
75
75
75
76
78
78
78
78
Contents
Page 4 of 78
Version 2.5
March 26, 2007
Datasheet
PowerPC 970FX RISC Microprocessor
List of Figures
Figure 1-1. PowerPC 970FX Block Diagram ................................................................................................ 15
Figure 1-2. Part Number Legend .................................................................................................................. 18
Figure 3-1. Clock Differential HSTL Signal ................................................................................................... 27
Figure 3-2. Processor-Clock Timing Relationship between PSYNC and SYSCLK ...................................... 29
Figure 3-3. Block Diagram of an SSB for a Processor Interconnect Implementation ................................... 30
Figure 3-4. Typical Implementation for a Single-Ended Line ........................................................................ 31
Figure 3-5. Differential Clock Termination Circuitry ...................................................................................... 32
Figure 3-6. Post-IAP Eye Opening ............................................................................................................... 33
Figure 3-7. Asynchronous Input Timing ........................................................................................................ 35
Figure 3-8. HRESET and BYPASS Timing Diagram .................................................................................... 38
Figure 3-9. Spread Spectrum Clock Generator Modulation Profile .............................................................. 40
Figure 3-10. JTAG Clock Input Timing Diagram ........................................................................................... 42
Figure 3-11. Test Access Port Timing Diagram ............................................................................................ 43
Figure 4-1. PowerPC 970FX Microprocessor Mechanical Package for Standard Lead DD3.0x Parts ........ 46
Figure 4-2. PowerPC 970FX Microprocessor Mechanical Package for Standard Lead, DD3.1x Parts ....... 47
Figure 4-3. PowerPC 970FX Microprocessor Bottom Dimensions for Standard Lead CBGA Package ....... 48
Figure 4-4. PowerPC 970FX Microprocessor Mechanical Package for Reduced-Lead DD3.0x Parts ........ 50
Figure 4-5. PowerPC 970FX Microprocessor Mechanical Package for Reduced-Lead DD3.1 Parts .......... 51
Figure 4-6. PowerPC 970FX Microprocessor Bottom Dimensions for Reduced-Lead CBGA Package ....... 52
Figure 4-7. PowerPC 970FX Ball Placement (Top View) ............................................................................. 53
Figure 4-8. PowerPC 970FX Ball Placement (Bottom View) ........................................................................ 54
Figure 5-1. PLL Power Supply Filter Circuit ................................................................................................. 66
Figure 5-2. Decoupling Capacitor Locations ................................................................................................ 68
Figure 5-3. PowerPC 970FX Thermal Diode Implementation ...................................................................... 76
Figure 5-4. Force Diagram for the PowerPC 970FX Package ..................................................................... 77
Version 2.5
March 26, 2007
List of Figures
Page 5 of 78
