Integrated
Circuit
Systems, Inc.
ICS843003
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
F
EATURES
• Three 3.3V LVPECL outputs on two banks, A Bank with
one LVPECL pair and B Bank with 2 LVPECL output pairs
• Using a 31.25MHz or 26.041666 crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 560MHz to 700MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.51ps (typical)
• RMS phase noise at 156.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -96.8 dBc/Hz
1KHz .............. -119.1 dBc/Hz
10KHz .............. -126.4 dBc/Hz
100KHz .............. -127.0 dBc/Hz
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
G
ENERAL
D
ESCRIPTION
The ICS843003 is a 3 differential output LVPECL
Synthesizer designed to generate Ethernet refer-
HiPerClockS™
ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 31.25MHz or
26.041666MHz, 18pF parallel resonant crystal, the following fre-
quencies can be generated based on the settings of 4 frequency
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz. The 843003 has 2 output
banks, Bank A with 1 differential LVPECL output pair and Bank
B with 2 differential LVPECL output pairs.
ICS
The two banks have their own dedicated frequency select pins
and can be independently set for the frequencies mentioned
above. The ICS843003 uses ICS’ 3rd generation low phase noise
VCO technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Ethernet jitter requirements. The ICS843003
is packaged in a small 24-pin TSSOP package.
P
IN
A
SSIGNMENT
DIV_SELB0
VCO_SEL
MR
V
CCO
_
A
QA0
nQA0
OEB
OEA
FB_DIV
V
CCA
V
CC
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
CCO
_
B
QB0
nQB0
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
V
EE
DIV_SELA1
B
LOCK
D
IAGRAM
OEA
Pullup
DIV_SELA[1:0]
VCO_SEL
Pullup
ICS843003
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
QA0
Top View
nQA0
TEST_CLK
Pulldown
0
00
01
0
10
11
÷1
÷2
(default)
÷4
÷5
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
625MHz
1
QB0
FB_DIV
0 = ÷20 (default)
1 = ÷24
00
01
10
11
÷1
÷2
÷4
(default)
÷5
nQB0
QB1
nQB1
FB_DIV
Pulldown
DIV_SELB[1:0]
MR
Pulldown
OEB
Pullup
843003AG
www.icst.com/products/hiperclocks.html
1
REV. A JULY 27, 2004
Integrated
Circuit
Systems, Inc.
ICS843003
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
Type
Description
Division select pin for Bank B. Default = Low.
Pulldown
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the cr ystal reference
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
Pullup
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state of
outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVPECL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the
output pair on Bank B is enabled. When logic LOW, the output pair drives
differential Low (QB0=Low, nQB0=High). Has an internal pullup resistor so
the default power-up state of outputs are enabled.
LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the
2 output pairs on Bank A are enabled. When logic LOW, the output pair
drives differential Low (QA0=Low, nQA0=High). Has an internal pullup
resistor so the default power-up state of outputs are enabled.
LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
for ÷20. When HIGH, the feedback divider is set for ÷24.
LVCMOS/LVTTL interface levels.
Analog supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
Name
DIV_SELB0
Input
2
VCO_SEL
Input
3
MR
Input
4
5, 6
V
CCO_A
QA0, nQA0
Power
Ouput
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12
13
14
15, 16
FB_DIV
V
CCA
V
CC
DIV_SELA0
DIV_SELA1
V
EE
XTAL_OUT,
XTAL_IN
TEST_CLK
Input
Power
Power
Input
Input
Power
Input
Pulldown
17
Input
18
19, 20
21, 22
23
XTAL_SEL
nQB1, QB1
nQB0, QB0
V
CCO_B
Input
Output
Output
Power
Core supply pin.
Division select pin for Bank A. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels.
Division select pin for Bank A. Default = Low.
Pulldown
LVCMOS/LVTTL interface levels.
Negative supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the cr ystal
circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
Pulldown pull to low state by default. Can leave floating if using the cr ystal interface.
LVCMOS/LVTTL interface levels.
Cr ystal select pin. Selects between the single-ended TEST_CLK or cr ystal
Pullup
interface. Has an internal pullup resistor so the cr ystal interface is selected
by default. LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pin for Bank B outputs.
Division select pin for Bank B. Default = High.
24
DIV_SELB1
Input
Pullup
LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
843003AG
www.icst.com/products/hiperclocks.html
2
REV. A JULY 27, 2004
Integrated
Circuit
Systems, Inc.
ICS843003
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
T
ABLE
3A. B
ANK
A F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
DIV_SELA1
0
0
1
1
0
0
1
1
DIV_SELA0
0
1
0
1
0
1
0
1
FB_DIV
0
0
0
0
1
1
1
1
Feedback
Divider
20
20
20
20
24
24
24
24
Bank A
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
4.8
QA0/nQA0
Output
Frequency
625
312.5
156.25
125
625
312.5
156.25
125
T
ABLE
3B. B
ANK
B F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
31.25
31.25
31.25
31.25
26.041666
26.041666
26.041666
26.041666
DIV_SELA1
0
0
1
1
0
0
1
1
DIV_SELA0
0
1
0
1
0
1
0
1
FB_DIV
0
0
0
0
1
1
1
1
Feedback
Divider
20
20
20
20
24
24
24
24
Bank B
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
20
10
5
4
24
12
6
4.8
QBx/nQBx
Output
Frequency
625
312.5
156.25
125
625
312.5
156.25
125
843003AG
www.icst.com/products/hiperclocks.html
3
REV. A JULY 27, 2004
Integrated
Circuit
Systems, Inc.
ICS843003
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
Outputs
QA
÷1
÷2
÷4
÷5
Inputs
DIV_SELB1
0
0
1
1
DIV_SELB0
0
1
0
1
Outputs
QB
÷1
÷2
÷4
÷5
T
ABLE
3C. O
UTPUT
B
ANK
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
T
ABLE
3D. F
EEDBACK
D
IVIDER
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
FB_DIV
0
1
Feedback Divide
÷20
÷24
Disabled
Enabled
TEST_CLK
OEA, OEB
nQA0, nQBx
QA0, QBx
F
IGURE
1. OE T
IMING
D
IAGRAM
843003AG
www.icst.com/products/hiperclocks.html
4
REV. A JULY 27, 2004
Integrated
Circuit
Systems, Inc.
ICS843003
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, TA = 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO_A, B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Included in I
EE
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
158
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_A
= V
CCO_B
= 3.3V±5%, TA = 0°C
TO
70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
DIV_SELA0:A1, FB_DIV
DIV_SELB0:B1, VCO_SEL,
Input
Low Voltage MR, OEA, OEB, XTAL_SEL
TEST_CLK
TEST_CLK, MR, FB_DIV
DIV_SELA1, DIV_SELB0
Input
High Current DIV_SELB1, DIV_SELA0,
VCO_SEL, XTAL_SEL,
OE A , O E B
TEST_CLK, MR, FB_DIV
DIV_SELA1, DIV_SELB0
Input
Low Current DIV_SELB1, DIV_SELA0,
VCO_SEL, XTAL_SEL,
OEA, OEB
Test Conditions
Minimum
2
-0.3
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Typical
Maximum
V
CC
+ 0.3
0.8
1.3
150
5
Units
V
V
V
µA
µA
µA
µA
I
IH
I
IL
843003AG
www.icst.com/products/hiperclocks.html
5
REV. A JULY 27, 2004
