PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85211
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
F
EATURES
•
2 differential LVHSTL compatible outputs
•
1 differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 600MHz
•
Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
•
Output skew: TBD
•
Part-to-part skew: TBD
•
Propagation delay: 900ps (typical)
•
V
OH
= 1.2V (maximum)
•
3.3V operating supply
•
0°C to 85°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS85211 is a low skew, high perfor-
mance 1-to-2 Differential-to-LVHSTL Fanout
HiPerClockS™
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The CLK, nCLK pair can accept most
standard differential input levels.T h e I C S 8 5 21 1 i s
characterized to operate from a 3.3V power supply.
Guaranteed output and part-to-part skew char-
acteristics make the ICS85211 ideal for those clock
distribution applications demanding well defined
performance and repeatability. For optimal performance,
terminate all outputs.
,&6
B
LOCK
D
IAGRAM
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
DD
CLK
nCLK
GND
CLK
nCLK
ICS85211
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
85211AM
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 3, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85211
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
Type
Output
Output
Power
Input
Input
Power
V
DD
/2
Description
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Power supply ground.
Inver ting differential clock input. V
DD
/2 default when left floating.
Positive supply pin.
Pulldown Non-inver ting differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
GND
nCLK
CLK
V
DD
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
51
51
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
KΩ
KΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
0
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0, Q1
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0, nQ1
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
85211AM
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 3, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85211
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
DD
Outputs, V
DD
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= 0°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
TBD
Units
V
mA
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= 0°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK
CLK
nCLK
CLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
4C. LVHSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= 0°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
1.0
0
0.4
0.8
Typical
Maximum
1.2
0.4
1.0
Units
V
V
V
NOTE 1: All outputs must be terminated with 50
Ω
to ground.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, T
A
= 0°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
200
IJ 600MHz
900
TBD
TBD
600
Test Conditions
Minimum
Typical
Maximum
600
Units
MHz
ps
ps
ps
ps
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle
50
%
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85211AM
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 3, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85211
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
=
3.3V±5%
Qx
SCOPE
V
DD
nCLK
LVHSTL
nQx
V
PP
Cross Points
V
CMR
CLK
GND
GND = 0V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQx
Qx
nQy
Qy
tsk(o)
D
IFFERENTIAL
I
NPUT
L
EVEL
Qx
PART 1
nQx
Qy
PART 2
nQy
tsk(pp)
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
nCLK
80%
80%
V
20%
Clock Outputs
t
R
SW I N G
CLK
nQ0, nQ1
Q0, Q1
t
PD
20%
t
F
O
UTPUT
R
ISE
/F
ALL
T
IME
nQ0, nQ1
Q0, Q1
Pulse Width
t
PERIOD
P
ROPAGATION
D
ELAY
odc =
t
PW
t
PERIOD
odc & t
P
ERIOD
85211AM
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 3, 2003
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS85211
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-LVHSTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
V
DD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
S
CHEMATIC
E
XAMPLE
Figure 2
shows a schematic example of ICS85211. In this
example, the input is driven by an ICS HiPerClockS LVHSTL
driver. The decoupling capacitors should be physically located
1.8V
Zo = 50 Ohm
5
6
7
8
near the power pin. For ICS85211, the unused outputs need
to be terminated.
Zo = 50 Ohm
U1
GND
nCLK
CLK
VDD
nQ1
Q1
nQ0
Q0
4
3
2
1
Zo = 50 Ohm
+
R1
50
R2
50
LVHSTL Input
-
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R6
50
R5
50
VDD=3.3V
C1
0.1u
ICS85211-03
Zo = 50 Ohm
-
Zo = 50 Ohm
+
R3
50
R4
50
LVHSTL Input
F
IGURE
2. ICS85211 LVHSTL B
UFFER
S
CHEMATIC
E
XAMPLE
85211AM
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5
REV. A JANUARY 3, 2003
