Integrated
Circuit
Systems, Inc.
ICS94220
Programmable System Clock Chip for AMD - K7™ Processor
Recommended Application:
VIA KX/KT133 style chipset
Output Features:
•
1 - Differential pair open drain CPU clocks
•
1 - CPU clock @ 3.3V
•
13 - SDRAM @ 3.3V
•
6 - PCI @3.3V,
•
1 - 48MHz, @3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
2 - REF @3.3V, 14.318MHz.
Features:
•
Programmable ouput frequency.
•
Programmable ouput rise/fall time.
•
Programmable PCI_F and PCICLK skew.
•
Real time system reset output
•
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
•
Uses external 14.318MHz crystal.
•
FS pins for frequency select
Pin Configuration
VDD1
REF0/CPU_STOP#*
GND
X1
X2
VDD2
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS2*
GND
CPUCLK
GND
CPUCLKC0
CPUCLKT0
VDDCPU
RESET#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24/48MHz/FS1*
48-Pin 300mil SSOP
*
Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
90.00
95.00
101.00
102.00
100.90
103.00
105.00
100.00
107.00
109.00
110.00
111.00
113.00
115.00
117.00
133.30
PCICLK
(MHz)
30.00
31.67
33.67
34.00
33.57
34.33
35.00
33.33
35.67
36.33
36.67
37.00
37.67
38.33
39.00
33.33
REF (1:0)
CPUCLK
CPU
DIVDER
Stop
CPUCLKC0
CPUCLKT0
SEL24_48#
SDATA
SCLK
FS (3:0)
CPU_STOP#
Control
Logic
Config.
Reg.
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
RESET#
SDRAM
DRIVER
SDRAM (11:0)
SDRAM_OUT
BUFFER IN
0443A—07/03/02
ICS94220
ICS94220
Pin Descriptions
PIN NUMBER
1
2
CPU_STOP#
1, 2
3,9,16,22,
33,39,45, 47
4
5
6,14
7
MODE
1, 2
8
10
13, 12, 11
15
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
19,30,36
23
24
25
26
27
40
41
42
43
44
46
48
FS3
1, 2
PCICLK0
SEL24_48#
1, 2
PCICLK1
PCICLK (4:2)
BUFFER IN
SDRAM (11:0)
VDD3
SDATA
SCLK
24_48MHz
FS1
1, 2
48MHz
FS0
1, 2
VDD4
SDRAM_OUT
RESET#
VDDCPU
CPUCLKT0
CPUCLKC0
CPUCLK
REF1
FS2
1, 2
IN
IN
OUT
IN
OUT
OUT
IN
OUT
PWR
IN
IN
OUT
IN
OUT
IN
PWR
OUT
OUT
PWR
OUT
OUT
OUT
OUT
IN
GND
X1
X2
VDD2
PCICLK_F
PIN NAME
VDD1
REF0
TYPE
DESCRIPTION
P W R REF, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the
OUT
STRONGER buffer for ISA BUS loads
This asynchronous input halts CPUCLKT, CPUCLKC & at logic
IN
"0" level when driven low.
PWR
IN
OUT
PWR
OUT
Ground
Cr ystal input, has inter nal load cap (36pF) and feedback
resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load
cap (36pF)
Supply for PCICLK_F and PCICLK, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock output
Logic input to select 24 or 48MHz for pin 25 output
PCI clock output.
PCI clock outputs.
Input to Fanout Buffers for SDRAM outputs.
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN
pin (controlled by chipset).
Supply for SDRAM nominal 3.3V.
Data input for I
2
C serial input, 5V tolerant input
Clock input of I
2
C input, 5V tolerant input
24MHz/48MHz clock output
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
Power for 24 & 48MHz output buffers and fixed PLL core.
Reference clock for SDRAM zero delay buffer
Real time system reset signal for watchdog timer timeout. This
signal is active low.
Supply for CPU clock 3.3V
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up.
3.3V CPU clock output powered by pin 42
14.318 MHz reference clock.
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0443A—07/03/02
2
ICS94220
General Description
The
ICS94220
is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
The
ICS94220
belongs to ICS new generation of programmable system clock generators. It employs serial
programming I
2
C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE, Pin 7
(Latched Input)
0
1
Pin 2
CPU_STOP#
(Input)
REF0
(Output)
0443A—07/03/02
0443A—07/03/02
3
ICS94220
General I
2
C serial interface information for the ICS94220
How to Write:
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending
Byte 0 through Byte 20
(see Note)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends
Byte 0 through byte 8 (default)
ICS clock sends
Byte 0 through byte X (if X
(H)
was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
ICS (Slave/Receiver)
How to Read:
Controlle r (Host)
Start Bit
Address D3
(H )
ICS (Sla ve /Re ce ive r)
ACK
ACK
A CK
Byte Count
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B8
ACK
Byte 7
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
If 12
H
has been written to B8
ACK
If 13
H
has been written to B8
ACK
If 14
H
has been written to B8
ACK
Stop Bit
Byte18
Byte 19
Byte 20
*See notes on the following page
.
0443A—07/03/02
4
ICS94220
Brief I
2
C registers description for ICS94220
Programmable System Frequency Generator
Register Name
Functionality &
Frequency Select
Register
Output Control Registers
Byte
0
Description
Output frequency, hardware / I C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00
H
to
this byte.
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
These registers control the spread
percentage amount.
Increment or decrement the group
skew amount as compared to the
initial skew.
These registers will control the
output rise and fall time.
2
PWD Default
See individual
byte
description
See individual
byte
description
See individual
byte
description
1-6
Vendor ID & Revision ID
Registers
7
Byte Count
Read Back Register
8
08
H
Watchdog Timer
Count Register
9
10
H
Watchdog Control
Registers
10 Bit [6:0]
000,0000
VCO Control Selection
Bit
10 Bit [7]
0
VCO Frequency Control
Registers
11-12
Depended on
hardware/byte
0 configuration
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
description
Spread Spectrum
Control Registers
Group Skews Control
Registers
Output Rise/Fall Time
Select Registers
13-14
15-16
17-20
Notes:
1.
2.
3.
4.
5.
6.
7.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol.
The number of bytes to
readback is defined by writing to byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set.
If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0443A—07/03/02
5
