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Integrated Device Technology, Inc.

FAST CMOS 16-BIT

REGISTERED/LATCHED

TRANSCEIVER WITH PARITY

IDT54/74FCT162511AT/CT

FEATURES:

•

0.5 MICRON CMOS Technology

Typical tsk(o) (Output Skew) < 250ps, clocked mode

Low input and output leakage

≤1µA

(max)

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,

15.7 mil pitch TVSOP and 25 mil pitch Cerpack

Extended commercial range of –40°C to +85°C

= 5V

±10%

Balanced Output Drivers:

±24mA

(commercial)

±16mA

(military)

Series current limiting resistors

Generate/Check, Check/Check modes

Open drain parity error allows wire-OR

DESCRIPTION:

The FCT162511AT/CT 16-bit registered/latched transceiver

with parity is built using advanced dual metal CMOS technol-

ogy. This high-speed, low-power transceiver combines D-

type latches and D-type flip-flops to allow data flow in transpar-

ent, latched or clocked modes. The device has a parity

generator/cheker in the A-to-B direction and a parity checker

in the B-to-A direction. Error checking is done at the byte level

with separate parity bits for each byte. Separate error flags

exits for each direction with a single error flag indicating an

error for either byte in the A-to-B direction and a second error

flag indicating an error for either byte in the B-to-A direction.

The parity error flags are open drain outputs which can be tied

together and/or tied with flags from other devices to form a

single error flag or interrupt. The parity error flags are enabled

by the

OExx

control pins allowing the designer to disable the

error flag during combinational transitions.

The control pins LEAB, CLKAB and

OEAB

control opera-

tion in the A-to-B direction while LEBA, CLKBA and

OEBA

control the B-to-A direction.

GEN

/CHK is only for the selection

of A-to-B operation, the B-to-A direction is always in checking

mode. The ODD/

EVEN

select is common between the two

directions. Except for the ODD/

EVEN

control, independent

operation can be achieved between the two directions by

using the corresponding control lines.

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM:

LEAB

CLKAB

Data

Parity

GEN/CHK

Byte

Parity

Generator/

Checker

Latch/

Parity, data

OEAB

B0-15

PB1,2

PERB

(Open Drain)

A0-15

PA1,2

ODD/EVEN

LEBA

CLKBA

Parity, data

OEBA

PERA

(Open Drain)

Latch/

Byte

Parity

Checking

Parity, Data

2916 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc.

AUGUST 1996

DSC–2916/5

5.11

IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM

ODD/EVEN

OEAB

LEBA

CLKBA

CLKAB

LEAB

- A

OEBA

- B

- A

- B

GEN/CHK

PERB

(Open Drain)

2916 drw 02

PERA

(Open Drain)

5.11

IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

OEAB

LEAB

GND

PERA

GND

OEBA

LEBA

GEN/CHK

CLKAB

GND

PERB

GND

CLKBA

ODD/EVEN

OEAB

LEAB

GND

PERA

GND

OEBA

LEBA

E56-1

GEN/CHK

CLKAB

GND

PERB

GND

CLKBA

ODD/EVEN

14 SO56-1 43

SO56-2

15 SO56-3 42

SSOP/

TSSOP/TVSOP

TOP VIEW

2916 drw 03

CERPACK

TOP VIEW

2916 drw 04

5.11

IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Description

Max.

TERM(2)

Terminal Voltage with Respect to –0.5 to +7.0

GND

TERM(3)

Terminal Voltage with Respect to

–0.5 to

GND

+0.5

STG

Storage Temperature

–65 to +150

OUT

DC Output Current

–60 to +120

Unit

°C

PIN DESCRIPTION

Pin Names

Description

A-to-B Output Enable Input (Active LOW)

B-to-A Output Enable Input (Active LOW)

A-to-B Latch Enable Input

B-to-A Latch Enable Input

A-to-B Clock Input

B-to-A Clock Input

A-to-B Data Inputs or B-to-A 3-State Outputs

B-to-A Data Inputs or A-to-B 3-State Outputs

Parity Error (Open Drain) on A Outputs

Parity Error (Open Drain) on B Outputs

A-to-B Parity Input, B-to-A Parity Output

B-to-A Parity Input, A-to-B Parity Output

Parity Mode Selection Input

A to B Port Generate or Check Mode Input

OEAB

OEBA

LEAB

LEBA

CLKAB

CLKBA

2916 lnk 01

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

2. Open drain and all device terminals except FCT162XXXT Output and I/O

terminals.

3. Output and I/O terminals for FCT162XXXT.

PERA

PERB

PAx

(1)

PBx

ODD/

EVEN

GEN

/CHK

FUNCTION TABLE

(1,4)

OEAB

Inputs

LEAB

CLKAB

↑

Outputs

(2)

(3)

2916 tbl 03

NOTES:

1. The PAx pin input is internally disabled during parity generation. This

means that when generating parity in the A to B direction there is no need

to add a pull up resistor to guarantee state. The pin will still function

properly as the parity output for the B to A direction.

NOTES:

2916 tbl 02

1. A-to-B data flow is shown. B-to-A data flow is similar but uses

OEBA

LEBA, and CLKBA.

2. Output level before the indicated steady-state input conditions were

established.

3. Output level before the indicated steady-state input conditions were

established, provided that CLKAB was HIGH before LEAB went LOW.

4. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don't Care

Z = High Impedance

↑

= LOW-to-HIGH Transition

5.11

IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

= +25°C, f = 1.0MHz)

Symbol

Parameter

(1)

Input

Capacitance

I/O

Capacitance

Open Drain

Capacitance

Conditions

= 0V

OUT

= 0V

OUT

= 0V

Typ.

3.5

Max.

6.0

8.0

6.0

Unit

2916 lnk 04

FUNCTION TABLE

(PARITY GENERATION)

(1, 2, 3, 4, 5)

- A

, Total Number

of inputs that are high

1, 3, 5 or 7

0, 2, 4, 6 or 8

ODD/

EVEN

NOTE:

1. This parameter is measured at characterization but not tested.

FUNCTION TABLE

(PARITY CHECKING)

(1, 2, 3, 4)

- A

and PA

1 (5)

, Total Number

of inputs that are high

1, 3, 5, 7 or 9

0, 2, 4, 6 or 8

ODD/

EVEN

2916 tbl 06

NOTES:

1. Conditions shown are for

GEN

/CHK = L,

OEAB

= L,

OEBA

= H.

2. A-to-B parity checking is shown. B-to-A is capable of parity checking while

A-to-B is performing generation. B-to-A will not generate parity.

3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control

as an edge triggered clock.

4. Conditions shown are for the byte A

-A

. The byte A

-A

is similiar but

will output the parity on PB

5. The error flag

PERB

will remain in a high state during parity generation.

PERB

(6)

2916 tbl 05

NOTES:

1. Conditions shown are for

GEN

/CHK = H,

OEAB

= L,

OEBA

= H.

2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses

OEBA

= L,

OEAB

= H and errors will be indicated on

PERA

3. In parity checking mode the parity bits will be transmitted unchanged along

with the corresponding data regardless of parity errors. (PB

= PA

4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control

as an edge triggered clock.

5. Conditions shown are for the byte A

-A

and PA

. The byte A

-A

and

is similiar.

6. The parity error flag

PERB

is a combined flag for both bytes A

-A

and A

. If a parity error occurs on either byte

PERB

will go low.

PERB

is an

open drain output which must be externally pulled up to achieve a logic

HIGH.

5.11

参数对比

与IDT54FCT162511CTE相近的元器件有：IDT54FCT162511CTEB、IDT74FCT162511ATPV、IDT74FCT162511CTE、IDT74FCT162511ATPA、IDT74FCT162511ATPF、IDT74FCT162511ATE、IDT74FCT162511CTPA、IDT74FCT162511CTPF、IDT54FCT162511ATE。描述及对比如下：

型号	IDT54FCT162511CTE	IDT54FCT162511CTEB	IDT74FCT162511ATPV	IDT74FCT162511CTE	IDT74FCT162511ATPA	IDT74FCT162511ATPF	IDT74FCT162511ATE	IDT74FCT162511CTPA	IDT74FCT162511CTPF	IDT54FCT162511ATE
描述	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, CDFP56, CERPACK-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, SSOP-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, TSSOP-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, TVSOP-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, TSSOP-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, TVSOP-56	Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, CDFP56, 0.635 MM PITCH, CERPACK-56
零件包装代码	DFP	DFP	SSOP	DFP	TSSOP	SSOP	DFP	TSSOP	SSOP	DFP
包装说明	DFP,	CERPACK-56	SSOP-56	DFP,	TSSOP-56	TVSOP-56	DFP,	TSSOP-56	TVSOP-56	DFP,
针数	56	56	56	56	56	56	56	56	56	56
Reach Compliance Code	unknown	not_compliant	not_compliant	compliant	not_compliant	not_compliant	compliant	not_compliant	not_compliant	unknown
其他特性	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B	INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B
系列	FCT	FCT	FCT	FCT	FCT	FCT	FCT	FCT	FCT	FCT
JESD-30 代码	R-GDFP-F56	R-GDFP-F56	R-PDSO-G56	R-GDFP-F56	R-PDSO-G56	R-PDSO-G56	R-GDFP-F56	R-PDSO-G56	R-PDSO-G56	R-GDFP-F56
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0	e0	e0
长度	18.415 mm	18.415 mm	18.415 mm	18.415 mm	14 mm	11.3 mm	18.415 mm	14 mm	11.3 mm	18.415 mm
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
位数	16	16	16	16	16	16	16	16	16	16
功能数量	1	1	1	1	1	1	1	1	1	1
端口数量	2	2	2	2	2	2	2	2	2	2
端子数量	56	56	56	56	56	56	56	56	56	56
最高工作温度	125 °C	125 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	125 °C
最低工作温度	-55 °C	-55 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-55 °C
输出特性	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR	3-STATE WITH SERIES RESISTOR
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
封装代码	DFP	DFP	SSOP	DFP	TSSOP	TSSOP	DFP	TSSOP	TSSOP	DFP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK	FLATPACK	SMALL OUTLINE, SHRINK PITCH	FLATPACK	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	FLATPACK	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	FLATPACK
传播延迟（tpd）	5.5 ns	5.5 ns	5.6 ns	5.3 ns	5.6 ns	5.6 ns	5.6 ns	5.3 ns	5.3 ns	6 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2.413 mm	2.413 mm	2.794 mm	2.413 mm	1.2 mm	1.2 mm	2.413 mm	1.2 mm	1.2 mm	2.413 mm
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	MILITARY
端子面层	TIN LEAD	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	TIN LEAD	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	TIN LEAD	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)	TIN LEAD
端子形式	FLAT	FLAT	GULL WING	FLAT	GULL WING	GULL WING	FLAT	GULL WING	GULL WING	FLAT
端子节距	0.635 mm	0.635 mm	0.635 mm	0.635 mm	0.5 mm	0.4 mm	0.635 mm	0.5 mm	0.4 mm	0.635 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
宽度	9.652 mm	9.652 mm	7.5 mm	9.652 mm	6.1 mm	4.4 mm	9.652 mm	6.1 mm	4.4 mm	9.652 mm
负载电容（CL）	50 pF	50 pF	50 pF	50 pF	50 pF	-	50 pF	50 pF	-	50 pF
Base Number Matches	1	1	1	1	1	1	1	1	1	-
是否Rohs认证	-	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合	-
控制类型	-	INDEPENDENT CONTROL	INDEPENDENT CONTROL	-	INDEPENDENT CONTROL	INDEPENDENT CONTROL	-	INDEPENDENT CONTROL	INDEPENDENT CONTROL	-
计数方向	-	BIDIRECTIONAL	BIDIRECTIONAL	-	BIDIRECTIONAL	BIDIRECTIONAL	-	BIDIRECTIONAL	BIDIRECTIONAL	-
最大I（ol）	-	0.016 A	0.024 A	-	0.024 A	0.024 A	-	0.024 A	0.024 A	-
封装等效代码	-	FL56,.4,25	SSOP56,.4	-	TSSOP56,.3,20	TSSOP56,.25,16	-	TSSOP56,.3,20	TSSOP56,.25,16	-
峰值回流温度（摄氏度）	-	NOT SPECIFIED	225	225	240	240	225	240	240	-
电源	-	5 V	5 V	-	5 V	5 V	-	5 V	5 V	-
Prop。Delay @ Nom-Sup	-	4.5 ns	5 ns	-	5 ns	5 ns	-	4.2 ns	4.2 ns	-
处于峰值回流温度下的最长时间	-	NOT SPECIFIED	20	30	20	20	30	20	20	-
翻译	-	N/A	N/A	-	N/A	N/A	-	N/A	N/A	-
触发器类型	-	POSITIVE EDGE	POSITIVE EDGE	-	POSITIVE EDGE	POSITIVE EDGE	-	POSITIVE EDGE	POSITIVE EDGE	-