IDT70V7599S200BC,IDT70V7599S200BC pdf中文资料,IDT70V7599S200BC引脚图,IDT70V7599S200BC电路-Datasheet-电子工程世界

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HIGH-SPEED 3.3V 128K x 36

SYNCHRONOUS

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

.eatures:

PRELIMINARY

IDT70V7599S

128K x 36 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

–

64 independent 2K x 36 banks

– 4 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (12Gbps bandwidth)

– Fast 3.6ns clock to data out

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

.unctional Block Diagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CONTROL

LOGIC

MUX

2Kx36

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

0L-35L

I/O

CONTROL

MUX

2Kx36

MEMORY

ARRAY

(BANK 1)

MUX

I/O

CONTROL

I/O

0R-35R

10L

ADDRESS

DECODE

ADDRESS

DECODE

10R

BANK

DECODE

MUX

2Kx36

MEMORY

ARRAY

(BANK 63)

BANK

DECODE

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

MUX

TDI

TDO

JTAG

TMS

TCK

TRST

5626 drw 01

NOVEMBER 2001

DSC 5626/2

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Description:

The IDT70V7599 is a high-speed 128Kx36 (4Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent

2Kx36 banks. The device has two independent ports with separate

control, address, and I/O pins for each port, allowing each port to access

any 2Kx36 memory block not already accessed by the other port.

Accesses by the ports into specific banks are controlled via the bank

address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup

and hold times. The timing latitude provided by this approach allows

systems to be designed with very short cycle times. With an input data

unidirectional or bidirectional data flow in bursts. An automatic power down

feature, controlled by CE

and CE

, permits the on-chip circuitry of each

port to enter a very low standby power mode. The dual chip enables also

facilitate depth expansion.

The 70V7599 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controllable by the OPT pins. The power supply for

the core of the device(V

) remains at 3.3V. Please refer also to the

functional description on page 19.

Pin Configuration

(1,2,3,4)

11/08/01

A10

A11

A12

A13

A14

A15

A16

A17

19L

18L

TDO

B10

CLK

CNTEN

B11

B12

B13

B14

OPT

I/O

17L

B15

B16

B17

I/O

20R

I/O

18R

TDI

C10

ADS

C11

C12

C13

C14

DDQR

I/O

16L

I/O

15R

C15

C16

C17

DDQL

I/O

19R

DDQR

PL/

10L

D10

R/W

D11

D12

D13

D14

I/O

16R

I/O

15L

D15

D16

D17

I/O

22L

I/O

21L

I/O

20L

REPEA T

I/O

17R

DDQL

I/O

14L

I/O

14R

E14

E15

E16

E17

I/O

23L

I/O

22R

DDQR

I/O

21R

I/O

12L

I/O

13R

F14

F15

F16

I/O

13L

F17

DDQL

I/O

23R

I/O

24L

G14

I/O

12R

I/O

11L

DDQR

G15

G16

G17

I/O

26L

I/O

25L

I/O

24R

I/O

DDQL

I/O

10L

I/O

11R

I/O

26R

DDQR

I/O

25R

70V7599BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

H14

H15

H16

H17

J14

J15

J16

I/O

10R

J17

DDQL

K14

K15

DDQR

K16

K17

I/O

28R

I/O

27R

I/O

L14

DDQL

I/O

L15

L16

L17

I/O

29R

I/O

28L

DDQR

I/O

27L

I/O

M14

I/O

M15

M16

I/O

M17

DDQL

I/O

29L

I/O

30R

N14

I/O

N15

I/O

DDQR

N16

N17

I/O

31L

I/O

31R

I/O

30L

P10

P11

P12

P13

I/O

DDQL

I/O

P14

P15

P16

I/O

P17

I/O

32R

I/O

32L

DDQR

I/O

35R

TRST

R10

CLK

CNTEN

R11

R12

R13

I/O

R14

I/O

R15

R16

I/O

R17

I/O

33L

I/O

34R

TCK

T10

ADS

T11

T12

T13

T14

DDQL

I/O

DDQR

T15

T16

T17

I/O

33R

I/O

34L

DDQL

TMS

10R

U10

R/W

U12

U13

U14

I/O

U15

U16

I/O

U17

I/O

35L

P L/

OPT

I/O

5626 drw 02c

NOTES:

1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

70V7599BC

BC-256

(5)

256-Pin BGA

Top View

(6)

11/08/01

A10

A11

A12

A13

A14

A15

A16

TDI

CNTEN

B10

B11

B12

B13

B14

B15

B16

I/O

18L

TDO

R/W

REPEAT

C10

C11

C12

C13

C14

I/O

17L

C15

C16

I/O

18R

I/O

19L

10L

CLK

ADS

D10

D11

D12

D13

OPT

I/O

17R

I/O

16L

D14

D15

D16

I/O

20R

I/O

19R

I/O

20L

PL/FT

DDQL

DDQR

DDQL

DDQR

E10

E11

E12

E13

I/O

15R

I/O

15L

I/O

16R

E14

E15

E16

I/O

21R

I/O

21L

I/O

22L

DDQL

F10

F11

DDQR

I/O

13L

I/O

14L

I/O

14R

F12

F13

F14

F15

F16

I/O

23L

I/O

22R

I/O

23R

DDQL

G10

G11

G12

DDQR

G13

I/O

12R

I/O

13R

I/O

12L

G14

G15

G16

I/O

24R

I/O

24L

I/O

25L

DDQR

H10

H11

H12

DDQL

I/O

10L

I/O

11L

I/O

11R

H13

H14

H15

H16

I/O

26L

I/O

25R

I/O

26R

DDQR

J10

J11

J12

DDQL

I/O

J13

J14

I/O

10R

J15

J16

I/O

27L

I/O

28R

I/O

27R

DDQL

K10

K11

K12

DDQR

I/O

K13

K14

K15

I/O

K16

I/O

29R

I/O

29L

I/O

28L

DDQL

L10

L11

L12

DDQR

I/O

L13

L14

I/O

L15

I/O

L16

I/O

30L

I/O

31R

I/O

30R

DDQR

M10

M11

M12

DDQL

I/O

M13

M14

I/O

M15

M16

I/O

32R

I/O

32L

I/O

31L

DDQR

N10

N11

N12

DDQL

I/O

N13

N14

I/O

N15

I/O

N16

I/O

33L

I/O

34R

I/O

33R

PL/FT

DDQR

DDQL

DDQR

DDQL

P10

P11

P12

P13

I/O

P14

I/O

P15

P16

I/O

35R

I/O

34L

TMS

10R

CLK

ADS

R10

R11

R12

R13

I/O

R14

R15

I/O

R16

I/O

35L

TRST

R/W

REPEAT

T10

T11

T12

T13

OPT

T14

T15

T16

TCK

CNTEN

5626 drw 02d

NOTES:

1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

DDQR

I/O

18R

I/O

18L

PL/FT

TDI

TDO

10L

CLK

R/W

ADS

CNTEN

REPEAT

OPT

I/O

17L

I/O

17R

DDQR

11/08/01

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

100

101

102

103

104

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

70V7599DR

DR-208

(5)

208-Pin PQFP

Top View

(6)

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

NOTES:

1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 28mm x 28mm x 3.5mm.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

DDQL

I/O

35R

I/O

35L

PL/FT

TMS

TCK

TRST

10R

CLK

R/W

ADS

CNTEN

REPEAT

OPT

I/O

DDQL

5626 drw 02a

6.42

IDT70V7599S

High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

R/W

- BA

- A

10L

I/O

- I/O

35L

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQL

OPT

TDI

TDO

TCK

TMS

TRST

Right Port

R/W

- BA

- A

10R

I/O

- I/O

35R

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQR

OPT

Chip Enables

Read/Write Enable

Output Enable

Bank Address

(4)

Address

Data Input/Output

Clock

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Counter Repeat

(3)

Byte Enables (9-bit bytes)

Power (I/O Bus) (3.3V or 2.5V)

(1)

Option for selecting V

DDQX

(1,2)

Power (3.3V)

(1)

Ground (0V)

Test Data Input

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

5626 tbl 01

Names

NOTES:

1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX

must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

3. When

REPEAT

is asserted, the counter will reset to the last valid address loaded

via

ADS

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory

with the shared array that is not currently being accessed by the opposite port

(i.e., BA

- BA

≠

- BA

). In the event that both ports try to access the

same bank at the same time, neither access will be valid, and data at the two

specific addresses targeted by the ports within that bank may be corrupted (in

the case that either or both ports are writing) or may result in invalid output (in

the case that both ports are trying to read).

6.42