®
CMOS STATIC RAM
1 MEG (128K x 8-BIT)
IDT71024
Integrated Device Technology, Inc.
FEATURES:
• 128K x 8 advanced high-speed CMOS static RAM
• Equal access and cycle times
— Military: 15/17/20/25ns
— Commercial: 12/15/17/20ns
• Two Chip Selects plus one Output Enable pin
• Bidirectional inputs and outputs directly TTL-compatible
• Low power consumption via chip deselect
• Available in 32-pin Ceramic DIP, Plastic DIP, 300 and
400 mil Plastic SOJ, and LCC packages
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT71024 is a 1,048,576-bit high-speed static RAM
organized as 128K x 8. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology. This state-
of-the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71024 has an output enable pin which operates as
fast as 6ns, with address access times as fast as 12ns
available. All bidirectional inputs and outputs of the IDT71024
are TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used; no clocks or
refreshes are required for operation.
The IDT71024 is packaged in 32-pin 400 mil Ceramic DIP,
32-pin 400 mil Plastic DIP, 32-pin 300 mil Plastic SOJ, 32-pin
400 mil Plastic SOJ, and 32-pin 400 x 820 mil LCC packages.
FUNCTIONAL BLOCK DIAGRAM
A
0
•
•
•
A
16
ADDRESS
DECODER
•
•
•
1,048,576-BIT
MEMORY ARRAY
I/O
0
– I/O
7
8
¥
I/O CONTROL
8
8
WE
OE
CS1
CONTROL
LOGIC
2964 drw 01
CS2
The IDT Logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1994
Integrated Device Technology, Inc.
MAY 1994
DSC-1012/5
8.2
1
IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
SO32-2 27
SO32-3 26
P32-3 25
D32-2 24
L32-2
23
22
21
20
19
18
17
V
CC
A
15
CS2
WE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Com’l.
Mil.
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power
Dissipation
DC Output
Current
0 to +70
–55 to +125
–55 to +125
1.25
50
A
13
A
8
A
9
A
11
OE
T
A
T
BIAS
T
STG
P
T
I
OUT
–55 to +125
–65 to +135
–65 to +150
1.25
50
°C
°C
°C
W
mA
A
10
CS1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
2964 drw 02
DIP/SOJ/LCC
TOP VIEW
NOTES:
2964 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
TRUTH TABLE
(1,2)
INPUTS
WE
CS1
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, SOJ package)
I/O
High-Z
High-Z
High-Z
High-Z
High-Z
FUNCTION
Deselected–Standby (I
SB
)
Deselected–Standby (I
SB1
)
Deselected–Standby (I
SB
)
Deselected–Standby (I
SB1
)
Outputs Disabled
Read Data
Write Data
2964 tbl 01
CS2
X
X
L
V
LC
(3)
H
H
H
OE
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
8
8
Unit
pF
pF
X
X
X
X
H
H
L
H
V
HC
(3)
X
X
L
L
L
X
X
X
X
H
L
X
NOTE:
2964 tbl 03
1. This parameter is guaranteed by device characterization, but is not prod-
uction tested.
DATA
OUT
DATA
IN
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max.
5.5
0
Vcc+0.5
0.8
Unit
V
V
V
V
NOTES:
1. H = V
IH
, L = V
IL
, X = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
-0.2V.
3. Other inputs
≥V
HC
or
≤V
LC.
NOTE:
2964 tbl 04
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT71024
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
.
Parameter
Input Leakage Current
Output Leakage Current
Output LOW Voltage
Output HIGH Voltage
Test Condition
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS1
= V
IH
, CS2 = V
IL
, V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OH
= –4mA, V
CC
= Min.
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2964 tbl 05
8.2
2
IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5.0V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
– 0.2V)
71024S12
(3)
Symbol
I
CC
Parameter
Dynamic Operating Current, CS2
≥
V
IH
and
CS2
≥
V
IH
and
CS1
≤
V
IL
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
Standby Power Supply Current (TTL Level)
CS1
≥
V
IH
or CS2
≤
V
IL
, Outputs Open,
V
CC
= Max., f = f
MAX
(2)
Full Standby Power Supply Current
(CMOS Level)
CS1
≥
V
HC,
or CS2
≤
V
LC
Outputs Open,
V
CC
= Max., f = 0
(2)
, V
IN
≤
V
LC
or V
IN
≥
V
HC
160
—
71024S15
155
180
71024S17
150
170
71024S20
140
160
71024S25
Com'l. Mil.
—
145
Unit
mA
Com'l. Mil. Com'l. Mil. Com'l.
Mil. Com'l. Mil.
I
SB
35
—
35
40
35
40
35
40
—
35
mA
I
SB1
15
—
10
15
10
15
10
15
—
15
mA
NOTES:
1.All values are maximum guaranteed values.
2.f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
3. 12ns specification is preliminary.
2964 tbl 06
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
2964 tbl 07
5V
480
Ω
DATA
OUT
30pF
255
Ω
2964 drw 03
5V
480
Ω
DATA
OUT
5pF*
255
Ω
2964 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
8.2
3
IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, All Temperature Ranges)
Symbol
Parameter
71024S12
(1)
Min. Max.
71024S15
Min. Max.
71024S17
71024S20 71024S25
(2)
Min.
Max. Min. Max. Min. Max.
Unit
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ(3)
t
CHZ(3)
t
OE
t
OLZ(3)
t
OHZ(3)
t
OH
t
PU(3)
t
PD(3)
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
12
—
—
3
0
—
0
0
4
0
—
—
12
12
—
6
6
—
5
—
—
12
15
—
—
3
0
—
0
0
4
0
—
—
15
15
—
7
7
—
5
—
—
15
17
—
—
3
0
—
0
0
4
0
—
—
17
17
—
8
8
—
6
—
—
17
20
—
—
3
0
—
0
0
4
0
—
—
20
20
—
8
8
—
7
—
—
20
25
—
—
3
0
—
0
0
4
0
—
—
25
25
—
10
10
—
10
—
—
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW(3)
t
WHZ(3)
Write Cycle Time
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Output Active from End-of-Write
Write Enable to Output in High-Z
12
10
10
0
10
0
7
0
3
0
—
—
—
—
—
—
—
—
—
5
15
12
12
0
12
0
8
0
3
0
—
—
—
—
—
—
—
—
—
5
17
13
13
0
13
0
9
0
3
0
—
—
—
—
—
—
—
—
—
7
20
15
15
0
15
0
9
0
4
0
—
—
—
—
—
—
—
—
—
8
25
15
15
0
15
0
10
0
4
0
—
—
—
—
—
—
—
—
—
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2964 tbl 08
NOTES:
1. 0°C to +70°C temperature range only. 12ns specification is preliminary.
2. –55°C to +125°C temperature range only.
3. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
8.2
4
IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS1
t
OLZ
(5)
CS2
t
CLZ
(5)
DATA
OUT
Vcc
SUPPLY
CURRENT
Icc
Isb
HIGH IMPEDANCE
t
PU
t
ACS
(3)
t
OHZ
(5)
t
CHZ
(5)
DATA
OUT
VALID
t
PD
2964 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
2964 drw 07
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS1
is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of
CS1
transition LOW and CS2 transition HIGH; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state.
8.2
5
