LOW POWER 3V CMOS SRAM
1 MEG (64K x 16-BIT)
Integrated Device Technology, Inc.
ADVANCE
INFORMATION
IDT71L016
FEATURES:
•
•
•
•
•
•
•
64K x 16 Organization
Wide Operating Voltage Range: 2.7V to 3.6V
Speed Grades: 70ns, 100ns
Low Operating Power: 45mA (max)
Low Standby Power: 5µA (max)
Low-Voltage Data Retention: 1.5V (min)
Available in a 44-pin TSOP package
DESCRIPTION:
The IDT71L016 is a 1,048,576-bit very low-power Static
RAM organized as 64K x 16. It is fabricated using IDT’s high-
reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides
a cost-effective solution for low-power memory needs. It uses
a 6-transistor memory cell.
All input and output signals of the IDT71L016 are LVTTL-
compatible and operation is from a single extended-range
3.3V supply. This extended supply range makes the device
ideally suited for unregulated battery-powered applications.
Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71L016 is packaged in a JEDEC standard 44-pin
TSOP Type II.
FUNCTIONAL BLOCK DIAGRAM
OE
Output
Enable
Buffer
A0 - A15
Address
Buffers
Row / Column
Decoders
I/O 15
Chip
Enable
Buffer
8
High
Byte
I/O
Buffer
8
CS
I/O 8
WE
Write
Enable
Buffer
64K x 16
Memory
Array
16
Sense
Amps
and
Write
Drivers
I/O 7
8
Low
Byte
I/O
Buffer
8
I/O 0
BHE
Byte
Enable
Buffers
BLE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3771 drw 01
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997
Integrated Device Technology, Inc.
MAY 1997
DSC-3771/2
1
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O 0
I/O 1
I/O 2
I/O 3
V
DD
V
SS
I/O 4
I/O 5
I/O 6
I/O 7
WE
I/O 15
I/O 14
I/O 13
I/O 12
V
SS
V
DD
I/O 11
I/O 10
I/O 9
I/O 8
NC
A8
A9
A10
A11
NC
3771 drw 02
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
A15
A14
A13
A12
NC
NOTE:
3771 tbl 06
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
TSOP
TOP VIEW
PIN DESCRIPTIONS
A
0
– A
15
CS
WE
OE
BHE
BLE
Address Inputs
Chip Select
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
Power
Ground
Input
Input
Input
Input
Input
Input
I/O
Pwr
Gnd
3771 tbl 01
I/O
0
- I/O
15
V
DD
V
SS
TRUTH TABLE
(1)
CS
OE
WE
BLE
BHE
I/O
0
-I/O
7
High-Z
DATA
OUT
High-Z
DATA
OUT
DATA
IN
DATA
IN
High-Z
High-Z
High-Z
I/O
8
-I/O
15
High-Z
High-Z
DATA
OUT
DATA
OUT
DATA
IN
High-Z
DATA
IN
High-Z
High-Z
Function
Deselected - Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
3771 tbl 02
H
L
L
L
L
L
L
L
L
X
L
L
L
X
X
X
H
X
X
H
H
H
L
L
L
H
X
X
L
H
L
L
L
H
X
H
X
H
L
L
L
H
L
X
H
NOTE:
1.H = V
IH
, L = V
IL
, X = Don't care.
2
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to V
SS
Terminal Voltage with
Respect to V
SS
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l. and Ind'l.
–0.5 to +4.6
–0.5 to V
DD
+0.5V
–55 to +125
–55 to +125
1.0
20
Unit
V
V
°C
°C
W
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
SS
0V
0V
V
DD
2.7V to 3.6V
2.7V to 3.6V
3771 tbl 04
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.7
0
2.0
–0.3
(2)
Typ.
3.0
0
—
—
Max.
3.6
0
V
DD
+0.3
(1)
NOTES:
3771 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. Input, Output,and I/O terminals; 4.6V maximum.
Unit
V
V
V
V
0.8
NOTE:
3771 tbl 05
1. V
IH
(max.) = V
DD
+ 1.5V for pulse width less than 5ns, once per cycle.
2. V
IL
(min.) = –1.5V for pulse width less than 5ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
V
DD
= 2.7V to 3.6V, Commercial and Industrial Temperature Ranges
Symbol
|I
LI
|
|I
LO
|
V
OH
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Test Conditions
V
DD
= Max., V
IN
= V
SS
to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= V
SS
to V
DD
I
OH
= –1mA, V
DD
= Min.
I
OL
= 2mA, V
DD
= Min.
Min.
—
—
2.4
—
Max.
1
1
—
0.4
Unit
µA
µA
V
V
3771 tbl 07
DC ELECTRICAL CHARACTERISTICS
(1, 2)
V
DD
= 2.7 to 3.6V, V
LC
= 0.2V, V
HC
= V
DD
–0.2V, Commercial and Industrial Temperature Ranges
Symbol
I
CC2
Parameter
Dynamic Operating Current
CS
Test Conditions
= V
LC
, Outputs Open,
-70 ns
-100 ns
V
DD
= 3.6V, f = f
MAX
(3)
Typ.
(5)
—
—
—
-40 to 85°C
0 to 70°C
40°C
25°C
—
—
—
—
Max.
45
35
10
10
5
2
1
Unit
mA
I
CC
I
SB1
Static Operating Current
Standby Supply Current
CS
= V
LC
, Outputs Open,
(4)
WE
= V
HC
, V
DD
= 3.6V, f = 0
= V
HC
, Outputs Open,
mA
µA
CS
V
DD
= 3.6V
NOTES:
1. All values are maximum guaranteed values.
2. Input low and high voltage levels are 0.2V and V
DD
-0.2V respectively for all tests.
3. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
).
4. f = 0 means no address input lines are changing .
5. Typical conditions are V
DD
= 3.0V and specified temperature.
3771 tbl 08
3
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(V
LC
= 0.2V, V
HC
= V
DD
- 0.2V)
Symbol
V
DR
I
CCDR
t
CDR(3)
t
R(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CS
Test Condition
—
≥
V
HC
Min.
1.5
—
0
t
RC(2)
Typ.
(1)
—
<1
—
—
Max.
—
5
—
—
Unit
V
µA
ns
ns
3771 tbl 09
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
LOW V
DD
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
V
DD
t
CDR
CS
2.7V
V
DR
≥
1.5V
V
IH
2.7V
t
R
V
IH
3771 drw 05
V
DR
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 2.5V
3ns
1.5V
1.5V
See Figure 1
3771 tbl 09
AC TEST LOAD
V
DD
3070Ω
DATA
OUT
50pF*
3150Ω
3771 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
4
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 2.7 to 3.6V, All Temperature Ranges)
71L016L70
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ(1)
t
CHZ(1)
t
OE
t
OLZ(1)
t
OHZ(1)
t
OH
t
BE
t
BLZ(1)
t
BHZ(1)
Write Cycle
t
WC
t
AW
t
CW
t
BW
t
AS
t
WR
t
WP
t
DW
t
DH
t
OW(1)
t
WHZ(1)
Write Cycle Time
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
Address Hold from End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
70
65
65
65
0
0
55
30
0
5
—
—
—
—
—
—
—
—
—
—
—
25
100
80
80
80
0
0
70
40
0
5
—
—
—
—
—
—
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3771 tbl 10
71L016L100
Min.
100
—
—
10
—
—
5
—
15
—
5
—
Max.
—
100
100
—
30
50
—
30
—
50
—
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
Min.
70
—
—
10
—
—
5
—
10
—
5
—
Max.
—
70
70
—
25
35
—
25
—
35
—
25
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1
(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3771 drw 06
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3.
OE
,
BHE
, and
BLE
are LOW.
5
