RETRANSMIT; AUTO POWER DOWN; ASYNCHRONOUS MODE IS ALSO POSSIBLE
最大时钟频率 (fCLK)
133.3 MHz
周期时间
7.5 ns
JESD-30 代码
S-PBGA-B144
JESD-609代码
e0
长度
13 mm
内存密度
2359296 bi
内存集成电路类型
OTHER FIFO
内存宽度
36
湿度敏感等级
3
功能数量
1
端子数量
144
字数
65536 words
字数代码
64000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
64KX36
可输出
YES
封装主体材料
PLASTIC/EPOXY
封装代码
BGA
封装等效代码
BGA144,12X12,40
封装形状
SQUARE
封装形式
GRID ARRAY
并行/串行
PARALLEL
峰值回流温度（摄氏度）
225
电源
3.3 V
认证状态
Not Qualified
座面最大高度
1.97 mm
最大待机电流
0.015 A
最大压摆率
0.04 mA
最大供电电压 (Vsup)
3.45 V
最小供电电压 (Vsup)
3.15 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn63Pb37)
端子形式
BALL
端子节距
1 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
20
宽度
13 mm
Base Number Matches
1
文档预览
3.3 VOLT HIGH-DENSITY SUPERSYNC II™
36-BIT FIFO
65,536 x 36
131,072 x 36
IDT72V36100
IDT72V36110
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
Choose among the following memory organizations:
IDT72V36100
65,536 x 36
IDT72V36110
131,072 x 36
Higher density, 2Meg and 4Meg SuperSync II FIFOs
Up to 166 MHz Operation of the Clocks
User selectable Asynchronous read and/or write ports (PBGA Only)
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
5V input tolerant
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
•
•
•
•
•
•
•
•
•
•
•
•
•
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
JTAG port, provided for Boundary Scan function (PBGA Only)
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic
Ball Grid Array (PBGA) (with additional features)
Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/
72V3670/72V3680/72V3690) family
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
°
°
FUNCTIONAL BLOCK DIAGRAM
*Available on the PBGA package only.
D
0
-D
n
(x36, x18 or x9)
WEN
WCLK/WR
LD SEN
*
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
*
ASYW
WRITE CONTROL
LOGIC
RAM ARRAY
65,536 x 36
131,072 x 36
WRITE POINTER
FLAG
LOGIC
READ POINTER
BE
IP
BM
IW
OW
MRS
PRS
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
ASYR
*
RCLK/RD
*
*
**
*
TCK
TRST
TMS
TDI
TDO
JTAG CONTROL
(BOUNDARY
SCAN)
*
OE
Q
0
-Q
n
(x36, x18 or x9)
REN
*
6117 drw01
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
SEPTEMBER 2003
DSC-6117/10
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION:
The IDT72V36100/72V36110 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls and a
flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key
user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 4 Mbit
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (D
n
) and a data output port (Q
n
), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
PIN CONFIGURATIONS
WCLK
PRS
MRS
LD
FWFT/SI
FF/IR
V
CC
PAF
GND
OW
FS0
HF
GND
FS1
BE
IP
BM
V
CC
PAE
PFM
EF/OR
RM
GND
RCLK
REN
RT
INDEX
WEN
SEN
DNC
(1)
V
CC
DNC
(1)
IW
D35
D34
D33
D32
V
CC
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
V
CC
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
V
CC
D12
GND
D11
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
D10
D9
D8
D7
D6
GND
D5
D4
D3
V
CC
D2
D1
D0
GND
Q0
Q1
Q2
Q3
Q4
Q5
GND
Q6
V
CC
Q7
Q8
Q9
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
OE
V
CC
V
CC
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
V
CC
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
V
CC
V
CC
Q15
Q14
Q13
Q12
GND
Q11
Q10
6117 drw02
NOTE:
1. DNC = Do Not Connect.
TQFP (PK128-1, order code: PF)
TOP VIEW
2
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
WCLK when
WEN
is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the
WEN
input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when
REN
is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the
REN
input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the
OE
input used
to provide three-state control of the outputs, Qn.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to f
MAX
with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In
IDT Standard mode,
the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
PIN CONFIGURATIONS (CONTINUED)
A1 BALL PAD CORNER
A
ASYW
WEN
WCLK
PRS
PAF
LD
FF/IR
MRS
HF
BM
EF
ASYR
BE
RCLK
IP
PAE
REN
OE
RT
Q35
Q34
B
SEN
IW
FS0
FS1
PFM
C
D35
D34
D33
FWFT/SI
OW
V
CC
V
CC
RM
Q32
D
D32
D31
D28
D30
D27
V
CC
V
CC
V
CC
GND
GND
GND
GND
GND
V
CC
GND
V
CC
V
CC
Q29
Q26
Q30
Q27
Q3
3
Q31
Q28
E
D29
F
D26
D25
D24
V
CC
V
CC
GND
GND
GND
GND
V
CC
V
CC
Q23
Q24
Q25
G
D21
D22
D23
GND
GND
GND
GND
Q22
Q21
Q20
H
D18
D19
D20
V
CC
GND
GND
GND
GND
V
CC
Q19
Q18
Q17
J
D15
D16
D17
V
CC
V
CC
GND
GND
V
CC
V
CC
Q16
Q13
Q15
Q12
Q14
K
D12
D13
D14
D3
D0
V
CC
V
CC
TDO
Q2
Q11
L
D10
D11
D8
D6
D7
D4
D5
D1
D2
TMS
TRST
TCK
TDI
Q0
Q1
Q3
Q4
Q5
Q6
Q10
Q7
Q9
Q8
M
D9
1
2
3
4
5
6
7
8
9
10
11
12
6117 drw02b
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
3
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
operation, which consists of activating
REN
and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In
FWFT mode,
the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on
REN
for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR
(Empty Flag or Output Ready),
FF/IR
(Full Flag or Input Ready),
HF
(Half-full Flag),
PAE
(Programmable
Almost-Empty flag) and
PAF
(Programmable Almost-Full flag). The
EF
and
FF
functions are selected in IDT Standard mode. The
IR
and
OR
functions are
selected in FWFT mode.
HF, PAE
and
PAF
are always available for use,
irrespective of timing mode.
PAE
and
PAF
can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that
PAE
can be set to switch at a predefined number of locations
from the empty boundary and the
PAF
threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and
LD
pins.
For serial programming,
SEN
together with
LD
on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming,
WEN
together with
LD
on each rising edge of WCLK, are used
to load the offset registers via D
n
.
REN
together with
LD
on each rising edge
of RCLK can be used to read the offsets in parallel from Q
n
regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect.
PRS
is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the
PAE
(Programmable Almost-
Empty flag) and
PAF
(Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the
PAE
and
PAF
flags.
PARTIAL RESET (PRS)
WRITE CLOCK (WCLK/WR*)
WRITE ENABLE (WEN)
LOAD (LD)
(x36, x18 or x9) DATA IN (D
0
- D
n
)
SERIAL ENABLE(SEN)
SERIAL CLOCK (SCLK)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
MASTER RESET (MRS)
READ CLOCK (RCLK/RD*)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
72V36100
72V36110
(x36, x18 or x9) DATA OUT (Q
0
- Q
n
)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
INPUT WIDTH (IW) BUS- OUTPUT WIDTH (OW)
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
4
6117 drw03
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
65,536 x 36 and 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If asynchronous
PAE/PAF
configuration is selected, the
PAE
is asserted
LOW on the LOW-to-HIGH transition of RCLK.
PAE
is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the
PAF
is asserted LOW on the LOW-
to-HIGH transition of WCLK and
PAF
is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF
configuration is selected , the
PAE
is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF
is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during Master Reset by the state of the Programmable Flag
Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the
RT
input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero latency retransmit operation is selected, the first data word to be
retransmitted will be placed on the output register with respect to the same RCLK
edge that initiated the retransmit based on RT being LOW.
Refer to Figure 11 and 12 for
Retransmit Timing
with normal latency. Refer
to Figure 13 and 14 for
Zero Latency Retransmit Timing.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x36/x18) and read
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
be read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the long word written into the
FIFO will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 4 for
Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D
0
-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin. Interspersed Parity control only has an
effect during parallel programming of the offset registers. It does not effect the data
written to and read from the FIFO.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V36100/72V36110 are fabricated using IDT’s high speed
