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IDT77V126L200

Single Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications

厂商名称:IDT(艾迪悌)

厂商官网:http://www.idt.com/

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Single Port PHY (Physical Layer)
for 25.6, 51.2, and 204.8 Mbps
ATM Networks and Backplane
Applications
IDT77V126L200
Features
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Description
The IDT77V126L200 is a member of IDT's family of products
supporting Asynchronous Transfer Mode (ATM) data communications
and networking. The IDT77V126L200 implements the physical layer for
25.6 Mbps ATM, connecting a serial copper link (UTP Category 3 and 5)
to an ATM layer device such as a SAR or a switch ASIC. The
IDT77V126L200 also operates at 51.2 and 204.8 Mbps and is well
suited to backplane driving applications. The 77V126L200 utilizes an 8-
bit UTOPIA1 interface on the cell side.
The IDT77V126L200 is fabricated using IDT's state-of-the-artCMOS
technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.
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Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions of the
Physical Layer
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
Operates at 25.6, 51.2, 102.4, 204.8 Mbps data rates
Backwards Compatible with 77V106L25
8-bit UTOPIA Level 1 Interface
3-Cell Transmit & Receive FIFOs
Receiver Auto-Synchronization and Good Signal Indication
LED Interface for status signalling
Supports UTP Category 3 and 5 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
64-lead TQFP Package (10 x 10 mm)
Industrial Temperature Ranges
Applications
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Up to 204.8Mbps backplane transmission
Rack-to-rack short links
ATM Switches
Block Diagram
TXLED
TXREF
TXCLK
TXDATA 9
TXSOC
TXEN
TXCLAV
3 CELL FIFO
SCRAMBLER
Pseudo Random
Nibble Gener-
ator
PRNG
4B/5B
ENCODER
P/S
NRZI
Line
Driver
TXD+
TXD-
ALE
WR
RD
CS
AD[7:0]
INT
RESET
8
UTILITY
BUS
CONTROLLER
RESET
LOOP BACK
RXCLK
RXDATA
RXSOC
RXEN
RXCLAV
RXREF
Line
RXVR
9
3 CELL FIFO
DESCRAMBLER
5B/4B
DECODER
S/P
DNRZI
CLK
REC
RXD+
RXD-
77V106
77V126
OSC
RxLED
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc..
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2004 Integrated Device Technology, Inc. All rights reserved. Product specification subject to change without notice.
December 2004
DSC 6030/1
IDT77V126L200
77V126L200 Overview
The 77V126L200 is a physical layer interface chip for up to 200Mbps
data rate ATM network communications as defined by ATM Forum docu-
ment af-phy-040.000 and ITU-T I.432.5. The physical layer is divided
into a Physical Media Dependent sub layer (PMD) and Transmission
Convergence (TC) sub layer. The PMD sub layer includes the functions
for the transmitter, receiver and clock recovery for operation across 100
meters of category 3 and 5 unshielded twisted pair (UTP) cable. This is
referred to as the Line Side Interface. The TC sub layer defines the line
coding, scrambling, data framing and synchronization.
On the cell side, the 77V126L200 connects to an ATM layer device
(such as a switch core or SAR) through an 8-bit Utopia Level 1 interface.
The 77V126L200 is based on the 77105 and maintains significant
register compatibility with it, but it also has additional register features.
Access to these status and control registers is through the utility bus.
This is an 8-bit muxed address and data bus, controlled by a conven-
tional asynchronous read/write handshake.
Additional pins permit insertion and extraction of an 8kHz timing
marker, and provide LED indication of receive and transmit status.
Auto-Synchronization and Good Signal
Indication
The 77V126L200 features a new receiver synchronization algorithm
that allow it to achieve 4b/5b symbol framing on any valid data stream.
This is an improvement on earlier products which could frame only on
the escape symbol, which occurs only in start-of-cell or 8kHz (X8) timing
marker symbol pairs.
ATM25 transceivers always transmit valid 4b/5b symbols, allowing
the 77V126L200 receive section to achieve symbol framing and properly
indicate receive signal status, even in the absence of ATM cells or 8kHz
(X8) timing markers in the receive data stream. A state machine moni-
tors the received symbols and asserts the “Good Signal” status bit when
a valid signal is being received. “Good Signal” is deasserted and the
receive FIFO is disabled when the signal is lost. This is sometimes
referred to as Loss of Signal (LOS).
Operation at Speeds Greater Than 25 Mbps
In addition to operation at the standard rate of 25.6 Mbps, the
77V126L200 is also specified to operate at 51.2 and 204.8 Mbps.
Except for the higher bit rates, all other aspects of operation are identical
to the 25.6 Mbps mode.
The rate is determined by the frequency of the clock applied to the
OSC input pin. OSC is 32 MHz for the 25.6 Mbps line rate, and 64 MHz
for the 51.2 and 204.8 Mbps line rate.
See Figure 16 for recommended line magnetics. Magnetics for 51.2
Mbps operation have a higher bandwidth than magnetics optimized for
25.6 Mbps. For 204.8Mbps data rate applications, ST6200T magnetics
from Pulse Engineering can be used. These magnetics have been
tested to work over 10 meters of UTP 5 cable at 204.8Mbps. Table 1
shows some of the different data rates the PHY can operate at using a
32MHz or 64MHz oscillator. Note that any oscillator frequency between
32MHz and 64MHz can be used. For example, if a 48MHz oscillator is
used and the multiplier is set to 4x, the data rate would be 153.6Mbps.
Reference
Clock (OSC)
32 MHz
Clock Multiplier
Control Bits
(Enhanced Control 2
Registers)
00 (1x)
01 (2x)
10 (4x)
Line Bit
Rate
(MHz)
32
64
128
64
128
256
Data
Rate
(Mbps)
25.6
51.2
102.4
51.2
102.4
204.8
64 MHz
00 (1x)
01 (2x)
10 (4x)
Table 1 200 Speed Grade Option
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December 2004
IDT77V126L200
RXREF
TXREF
TXLED
TXDATA0
TXDATA1
TXDATA2
TXDATA3
TXDATA4
TXDATA5
TXDATA6
TXDATA7
TXPARITY
TXEN
TXSOC
VDD
TXCLAV
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
Pin 1 Index
4
45
5
44
6
43
7
42
77V126
8
41
IDT77V106L200
9
40
10
39
11
38
12
37
36
13
14
35
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RXEN
RXCLAV
RXSOC
GND
RXPARITY
RXDATA7
RXDATA6
RXDATA5
RXDATA4
VDD
RXDATA3
RXDATA2
RXDATA1
RXDATA0
TXCLK
RXCLK
SM
VDD
TXD+
TXD-
GND
AVDD
RXD+
RXD-
AVDD
AGND
AVDD
AGND
OSC
AVDD
AGND
SE
AD7
AD6
AD5
AD4
GND
AD3
AD2
AD1
AD0
ALE
CS
RD
WR
RST
INT
RXLED
77v106 drw 02
77v106L200 drw 02
Figure 1 Pin Assignments
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December 2004
IDT77V126L200
Signal Descriptions
Line Side Signals
Signal Name
RXD+, RXD-
TXD+, TXD-
Pin Number
58, 57
62, 61
I/O
In
Out
Signal Description
Positive and negative receive differential input pair.
Positive and negative transmit differential output pair.
Utility Bus Signals
Signal Name
AD[7:0]
Pin Number
48, 47, 46,
45, 43, 42,
41, 40
39
38
37
36
I/O
In/
Out
In
In
In
In
Signal Description
Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this bus when a read
is performed. Input data is sampled at the completion of a write operation.
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling edge of ALE. ALE
must be low when the AD bus is being used for data.
Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain asserted at all
times if desired.
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by deasserting WR
and asserting RD and CS.
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by deasserting RD,
placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is deasserted.
Utopia Bus Signals
Signal Name
RXCLAV
RXCLK
Pin Number
20
18
I/O
Out
In
Out
Signal Description
"Utopia Receive Cell Available. "1" indicates that the receive FIFO contains a complete cell. "0" indicates that it does not.
Utopia Receive Clock. This is a free running clock input.
Utopia Receive Data. When one of the four ports is selected, the 77V126L200 transfers received cells to an ATM device
across this bus. Also see RXPARITY.
Utopia Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA bus.
Utopia Receive Data Parity. Odd parity over RXDATA[7:0].
Utopia Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA.
"Utopia Transmit Cell Available. "1" indicates that the transmit FIFO has room available for at least one complete cell. "0"
indicates that it does not.
Utopia Transmit Clock. This is a free running clock input.
Utopia Transmit Data. An ATM device transfers cells across this bus to the 77V126L200 for transmission. Also see TXPAR-
ITY.
Utopia Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA bus.
Utopia Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in the Interrupt Sta-
tus Registers, as enabled in the Master Control Register. No other action is taken in the event of an error. Tie high or low if
unused.
Utopia Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
Table 2 Signal Descriptions (Part 1 of 2)
ALE
CS
RD
WR
RXDATA[7:0] 24, 25, 26,
27, 29, 30,
31, 32
RXEN
RXPARITY
RXSOC
TXCLAV
TXCLK
TXDATA[7:0]
TXEN
TXPARITY
19
23
21
16
17
11, 10, 9, 8,
7, 6, 5, 4
13
12
In
Out
Out
Out
In
In
In
In
TXSOC
14
In
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December 2004
IDT77V126L200
Miscellaneous Signals
Signal Name
INT
OSC
RST
RXLED
RXREF
SE
SM
TXLED
TXREF
Pin Number
34
52
35
33
1
49
64
3
2
I/O
Out
In
In
Out
Out
In
In
Out
In
Signal Description
Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the interrupt status
in the appropriate interrupt Status Register is read. Interrupt sources are programmable via the interrupt Mask Registers.
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mbps; 64 MHz for 51.2 Mbps.
Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be performed after power up
prior to normal operation of the part.
Receive LED driver. Driven low for 223 cycles of OSC, beginning with RXSOC when a good (non-null and non-errored) cell
is received. Drives 8 mA both high and low.
Receive Reference. Active low. RXREF pulses low for a programmable number of clock cycles when an X_8 command byte
is received.
Reserved signal. This input must be connected to logic low.
Reserved signal. This input must be connected to logic low.
Transmit LED driver. Goes low for 223 cycles of OSC, beginning with TXSOC when a cell is received for transmission. 8 mA
drive current both high and low
Transmit Reference. At the falling edge of TXREF, an X_8 command byte is inserted into the transmit data stream. Typical
application is WAN timing.
Power Supply Signals
Signal Name
AGND
AVDO
GND
VDD
Pin Number
50, 53, 55
51, 54, 56,
59
22, 44, 60
15, 28, 63
I/O
Signal Description
Analog ground. AGND is ground the analog portion of the ship, which sources a more constant current than the digital por-
tion.
Analog power supply. AVDD supplies power to the analog portion of the chip, which draws a more constant current than the
digital portion. 3.3 + 0.3V
Digital Ground.
Digital power supply. 3.3 + 0.3V.
Table 2 Signal Descriptions (Part 2 of 2)
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December 2004
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参数对比
与IDT77V126L200相近的元器件有:IDT77V126L200TFI。描述及对比如下:
型号 IDT77V126L200 IDT77V126L200TFI
描述 Single Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Single Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications
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