SC654
Clock Generator for 3 DIMM, Pentium Boards
Preliminary Product Information
PRODUCT FEATURES
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Individual I
2
C clock stop controls for low power
mobile applications and EMI reduction
Designed to meet Intel
tm
specifications
Integrated crystal loading capacitors
Supports Intel Pentium, Pentium Pro, Pentium II,
Cyrix and AMD CPU’s
7 PCI BUS clocks (synchronous or asynchronous)
<250 pS skew on all CPU/SDRAM clocks
<500 pS between CPU and PCI clocks
2 Ref. Clocks @ 14.31818 MHz, one at VDDC
(IOAPIC)
Separate V
DDC
for CPUL (1:3) clock buffers and
IOAPIC
Programmable registers for jumperless frequency
selection
48 Pin SSOP Package
PRODUCT DESCRIPTION
The device is a high fanout EMI reducing system clock
generator that provides the large quantity of clocks needed to
support the motherboard. Bi-directional I/O pins are provided
to maximize the functionality of the device and provide the
input control features required for user flexibility.
FREQUENCY TABLE (MHz)
(Functionality with 14.31818 MHz input)
Frequency Select
CPUs
PCI (1:6)
FS2
FS1
FS0
MHz
BSEL = 1
BSEL = 0
0
0
0
60.0
30.0
32.0.
0
0
1
66.8
33.4
32.0
0
`1
0
50
25.0
32.0
0
1
1
55
27.5
32.0
1
0
0
75
37.5
32.0
1
0
1
68.7
34.4
32.0
1
1
0
83.3
41.7
32.0
1
1
1
Tri-state
Tri-state
Tri-state
BLOCK DIAGRAM
CONNECTION DIAGRAM
Xin
Xout
FS1
IMISC654
REF/FS1
VDD
REF/FS1
GND
XIN
XOUT
VDD
PCI1
PCI2
GND
PCI3
PCI4
PCI5
VDD
PCI6
PCI7/FS0
GND
SDR12
SDR11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
24M/BSEL
48M/FS2
GND
IOAPIC
CPUL1
CPUL2
VDDC
CPUL3
GND
SDR1
SDR2
VDDS
SDR3
SDR4
GND
SDR5
SDR6
VDDS
SDR7
SDR8
GND
CPUH1
CPUH2
OSC
FS2
PLL1
32M
48M/FS2
BSEL
24M/BSEL
IOAPIC
VDDC
CPUL (1:3)
PLL2
VDD
FS(0:2)
LATCH
CPUH(1:2)
SDR (1:12)
VDDS
SDATA
SCLK
CONTROL
LOGIC
E2
E3
/2
32MHz
BSEL
1
0
FS0
PCI (1:6)
PCI7/FS0
VDDS
SDR10
SDR9
GND
SDATA
SCLK
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/15/97
Page 1 of 11
SC654
Clock Generator for 3 DIMM, Pentium Boards
Preliminary Product Information
PIN DESCRIPTION
PIN
No.
4
Pin
Name
Xin
POWE
R
VDD
I/O
I
TYPE
OSC1
Description
On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal. Has internal 18 pF
crystal loading capacitor.
On-chip reference oscillator output pin. Drives an external
parallel resonant crystal. When an externally generated
reference signal is used, this pin is left unconnected. Has
internal 18 pF crystal loading capacitor.
Clock output. CPU frequency table specified. Power is
applied by VddC
Clock output. Low skew copy of the CPU clock used to
drive SDRAM clock pins.
5
Xout
VDD
O
OSC1
40, 42, 43
38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17
25, 26
7, 8, 10,
11, 12, 14
46
CPUL[1:3]
SDR
[1:12]
VDDC
VDDS
O
O
BUF1
BUF2
CPUH(1:2)
PCI [1:6]
48M/FS2
VDD
VDD
VDD
O
O
I/O
BUF1
BUF1
BUF 2
PU
BUF4
PU
BUF 2
PU
BUF3
PU
2
REF/FS1
VDD
I/O
47
24M/BSEL
VDD
I/O
15
PCI7/FS0
VDD
I/O
23
24
1,6, 13, 48
41
19, 30, 36
3, 9,16,22,
27,33,39,
45
44
SDATA
SCLK
VDD
VDDC
VDDS
GND
I
I
PWR
PWR
PWR
PWR
PAD
PU
PAD
PU
---
---
---
---
Clock output. Low skew copy of the CPU clock used to
drive SDRAM clock pins. Powered is applied by Vdd
Clock output. PCI Bus frequency table specified. Power is
applied by VDD Pins.
Bi-directional pin. During powerup sets the FS2 bit.
Afterwards, it is a 48.0 MHz output clock. Has internal
pullup.
Bi-directional pin. During powerup sets the FS1 bit.
Afterwards, it is a 14.31818 MHz reference output clock.
has internal pullup
Bi-directional pin. During powerup sets the bus mode
(BSEL) bit. Afterwards, it is a 24.0 MHz reference output
clock.
Bi-directional pin during power up. Its logic level is latched
and defines the selection of the frequency table. as FS0.
After power up it acts as a PCI clock output as defined by
the PCI [1:6] pins.
I
2
C data input pin Has internal pullup.
I
2
C clock input pin. Has internal pullup.
3.3 volt core, PCI clock and fixed clock power.
3.3 or 2.5 volt CPU clock power
3.3 volt power for SDRAM and CPUH buffers
Device ground
IOAPIC
VDDC
O
BUF4
This is a 14.31818 MHz clock. Its output buffers is supplied
by the VDDC and may be as 2.5 volts.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/15/97
Page 2 of 11
SC654
Clock Generator for 3 DIMM, Pentium Boards
Preliminary Product Information
Selection on Bi-directional Pins
Bi-directional pins and are used for selecting different functions in this device (see Pin description, Page 2). During power-up of the
device, these pins are in input mode and therefore, they are considered input select pins. Internal to the IC, these pins have a large
value pull-up each (100KΩ), therefore, a selection “1” is the default. If a selection “0” is desired, then a direct connection to ground
through a 10KΩ resistor should be implemented as shown in Fig.3. Please note the selection resistor (10KΩ) is placed before the
Damping resistor (Rd) and close to the devices pin.
Device
Bi-directional Pin
Rd
10KΩ
Fig. 3
To load
2-WIRE I
2
C CONTROL INTERFACE
The 2-wire control interface implements a write only slave interface. The device cannot be
read back. Sub-addressing is not supported, thus all preceding bytes must be sent in order to
change one of the control bytes. The 2-wire control interface allows each clock output to be
individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low,
and is stable when SDCLK is high. There are two exceptions to this. A high to low transition on
SDATA while SDCLK is high is used to indicate the start of a data transfer cycle. A low to high
transition on SDATA while SDCLK is high indicates the end of a data transfer cycle. Data is always
sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address
D2
by generating the
acknowledge (low) signal on the SDATA wire following reception of each byte. The device will not
respond to any other control interface conditions. Previously set control registers are retained.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/15/97
Page 3 of 11
SC654
Clock Generator for 3 DIMM, Pentium Boards
Preliminary Product Information
SERIAL CONTROL REGISTERS
NOTE:
The Pin# column lists the affected pin number where applicable. The @Pup column gives the state
at true power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command
Code
“ byte, and
2) “Byte
Count”
byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be
acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below
described sequence (Byte 0, Byte 1, Byte2, ....) will be valid and acknowledged.
Byte 0: CPU Clock Register (1
= enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
0
x
0
0
Pin#
*
*
*
*
*
n/a
*
*
Description
BSEL (frequency Table Selection via I
2
C)
FS2 (frequency Table Selection via I
2
C)
FS1 (frequency Table Selection via I
2
C)
FS0 (frequency Table Selection via I
2
C)
enable frequency selection by hardware (set to 0) or
software I
2
C (set to 1)
Reserved for future Spread Spectrum function
Bit 1 Bit 0
1
1 Tri-State
1
0
Reserved for IMI testing function
0
1
Test Mode
0
0
Normal
Function Table
Function
Description
Tri-State
Test (BSEL=1)
Test (BSEL=0)
Normal
Outputs
CPU
Hi-Z
Tclk/2
Tclk/2
see table
PCI
Hi-Z
Tclk/4
Tclk/3
see table
SDRAM
Hi-Z
Tclk/2
Tclk/2
CPU
REF
Hi-Z
Tclk
Tclk
14.318
IOAPIC
Hi-Z
Tclk
Tclk
14.318
Notes:
1. Tclk is a test clock over driven on the Xin input during test mode.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/15/97
Page 4 of 11
SC654
Clock Generator for 3 DIMM, Pentium Boards
Preliminary Product Information
SERIAL CONTROL REGISTERS (Cont.)
Byte 1: CPU, SIO, USB Clock Register (1
= enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
x
1
1
1
1
1
Pin#
46
47
-
25
26
40
42
43
Description
48 MHz enable/Stopped
24 MHz enable/Stopped
Reserved
CPUH2 enable/Stopped
CPUH1 enable/Stopped
CPUL3 enable/Stopped
CPUL2 enable/Stopped
CPUL1 enable/Stopped
Byte 2: PCI Clock Register
(1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
x
1
1
1
1
1
1
1
Pin#
-
15
14
12
11
10
8
7
Description
Reserved
PCI7 / FS0 enable/Stopped
PCI6 enable/Stopped
PCI5 enable/Stopped
PCI4 enable/Stopped
PCI3 enable/Stopped
PCI2 enable/Stopped
PCI1 enable/Stopped
Byte 3: SDRAM Clock Register
( 1 = enable, 0 = Stopped )
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
28
29
31
32
34
35
37
38
Description
SDRAM8 enable/Stopped
SDRAM7 enable/Stopped
SDRAM6 enable/Stopped
SDRAM5 enable/Stopped
SDRAM4 enable/Stopped
SDRAM3 enable/Stopped
SDRAM2 enable/Stopped
SDRAM1 enable/Stopped
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.2
4/15/97
Page 5 of 11
