PD -97140
IRFP4668PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
G
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
D
V
DSS
R
DS(on)
typ.
200V
8.0m
:
max. 9.7m
:
130A
S
I
D
D
G
D
S
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
c
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
e
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
Max.
130
92
520
520
3.5
± 30
57
-55 to + 175
300
10lbxin (1.1Nxm)
760
See Fig. 14, 15, 22a, 22b,
Units
A
W
W/°C
V
V/ns
°C
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
d
Avalanche Current
c
Repetitive Avalanche Energy
f
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θCS
R
θJA
Parameter
Junction-to-Case
j
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
ij
Typ.
–––
0.24
–––
Max.
0.29
–––
40
Units
°C/W
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1
9/8/08
IRFP4668PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
ΔV
(BR)DSS
/ΔT
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
200
–––
–––
3.0
–––
–––
–––
–––
–––
–––
0.21
8.0
–––
–––
–––
–––
–––
1.0
–––
–––
9.7
5.0
20
250
100
-100
–––
Conditions
V V
GS
= 0V, I
D
= 250μA
V/°C Reference to 25°C, I
D
= 5mAc
mΩ V
GS
= 10V, I
D
= 81A
f
V V
DS
= V
GS
, I
D
= 250μA
μA
V
DS
= 200V, V
GS
= 0V
V
DS
= 200V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
V
GS
= -20V
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Min. Typ. Max. Units
S
nC
Conditions
V
DS
= 50V, I
D
= 81A
I
D
= 81A
V
DS
= 100V
V
GS
= 10V
f
I
D
= 81A, V
DS
=0V, V
GS
= 10V
V
DD
= 130V
I
D
= 81A
R
G
= 2.7Ω
V
GS
= 10V
f
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 160V
h
V
GS
= 0V, V
DS
= 0V to 160V
g
150 ––– –––
––– 161 241
–––
54
–––
–––
52
–––
––– 109 –––
Turn-On Delay Time
–––
41
–––
Rise Time
––– 105 –––
Turn-Off Delay Time
–––
64
–––
Fall Time
–––
74
–––
Input Capacitance
––– 10720 –––
Output Capacitance
––– 810 –––
Reverse Transfer Capacitance
––– 160 –––
Effective Output Capacitance (Energy Related)h ––– 630 –––
––– 790 –––
Effective Output Capacitance (Time Related)g
ns
pF
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
c
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
–––
130
520
A
Conditions
MOSFET symbol
showing the
integral reverse
D
G
S
––– –––
1.3
V
––– 130 –––
ns
––– 155 –––
––– 633 –––
nC
––– 944 –––
–––
8.7
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 81A, V
GS
= 0V
f
T
J
= 25°C
V
R
= 100V,
I
F
= 81A
T
J
= 125°C
di/dt = 100A/μs
f
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.23mH
R
G
= 25Ω, I
AS
= 81A, V
GS
=10V. Part not recommended for
use above this value.
I
SD
≤
81A, di/dt
≤
520A/μs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400μs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
2
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IRFP4668PbF
1000
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
1000
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
10
BOTTOM
100
BOTTOM
1
≤60μs
PULSE WIDTH
Tj = 25°C
10
4.5V
0.1
4.5V
0.01
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
≤60μs
PULSE WIDTH
Tj = 175°C
1
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
Fig 2.
Typical Output Characteristics
3.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current
(Α)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
ID = 81A
VGS = 10V
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 50V
0.1
3.0
4.0
5.0
6.0
≤
60μs PULSE WIDTH
7.0
8.0
9.0
VGS, Gate-to-Source Voltage (V)
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
16000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Fig 4.
Normalized On-Resistance vs. Temperature
16
VGS, Gate-to-Source Voltage (V)
ID= 81A
VDS = 160V
VDS = 100V
VDS = 40V
12000
C, Capacitance (pF)
12
Ciss
8000
8
4000
Coss
0
1
Crss
10
VDS , Drain-to-Source Voltage (V)
100
4
0
0
40
80
120
160
200
QG Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFP4668PbF
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS (on)
ISD, Reverse Drain Current (A)
100
TJ = 175°C
1000
100μsec
100
10msec
10
1msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
DC
10
TJ = 25°C
1
VGS = 0V
0.1
0.0
0.5
1.0
1.5
VSD , Source-to-Drain Voltage (V)
0.1
10
100
1000
VDS , Drain-toSource Voltage (V)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
140
120
Fig 8.
Maximum Safe Operating Area
250
Id = 5mA
240
230
220
210
200
190
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
ID , Drain Current (A)
100
80
60
40
20
0
25
50
75
100
125
150
175
TC , CaseTemperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
14
12
10
Fig 10.
Drain-to-Source Breakdown Voltage
2500
2000
18A
24A
BOTTOM
81A
TOP
ID
Energy (μJ)
8
6
4
2
0
0
40
80
120
160
200
1500
1000
500
0
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFP4668PbF
1
Thermal Response ( Z thJC )
0.1
D = 0.50
0.20
0.10
0.01
0.05
0.02
0.01
τ
J
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
R
3
R
3
τ
C
τ
3
τ
Ri (°C/W)
τι
(sec)
τ
1
τ
2
τ
3
Ci=
τi/Ri
Ci=
τi/Ri
0.063359 0.000278
0.110878 0.005836
0.114838 0.053606
0.001
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
0.001
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔTj
= 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ
j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
10
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
800
EAR , Avalanche Energy (mJ)
600
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 81A
400
200
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
ΔT
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
175
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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