PD -
96186A
IRFS4010PbF
IRFSL4010PbF
HEXFET
®
Power MOSFET
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
D
G
S
V
DSS
R
DS(on)
typ.
max.
I
D
D
100V
3.9m
:
4.7m
:
180A
D
S
G
G
D
S
D
2
Pak
IRFS4010PbF
TO-262
IRFSL4010PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Max.
180
127
720
375
2.5
± 20
31
-55 to + 175
300
Units
A
W
W/°C
V
V/ns
c
e
°C
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
c
d
f
i
318
See Fig. 14, 15, 22a, 22b,
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
jk
Parameter
Typ.
–––
–––
Max.
0.40
40
Units
°C/W
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1
07/07/11
IRFS/SL4010PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
ΔV
(BR)DSS
/ΔT
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G(int)
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
Conditions
–––
0.10
3.9
–––
–––
–––
–––
–––
2.0
–––
–––
4.7
4.0
20
250
100
-100
–––
V V
GS
= 0V, I
D
= 250μA
V/°C Reference to 25°C, I
D
= 5mA
mΩ V
GS
= 10V, I
D
= 106A
V V
DS
= V
GS
, I
D
= 250μA
V
DS
= 100V, V
GS
= 0V
μA
V
DS
= 100V, V
GS
= 0V, T
J
= 125°C
V
GS
= 20V
nA
V
GS
= -20V
f
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
189
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
143
38
50
93
21
86
100
77
9575
660
270
757
1112
–––
215
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
V
DS
= 25V, I
D
= 106A
I
D
= 106A
V
DS
= 50V
V
GS
= 10V
I
D
= 106A, V
DS
=0V, V
GS
= 10V
V
DD
= 65V
I
D
= 106A
R
G
= 2.7Ω
V
GS
= 10V
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz See Fig.5
V
GS
= 0V, V
DS
= 0V to 80V See Fig.11
V
GS
= 0V, V
DS
= 0V to 80V
f
ns
f
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
g
h
pF
h
g
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Min. Typ. Max. Units
–––
–––
–––
–––
180
A
720
Conditions
MOSFET symbol
showing the
integral reverse
G
S
D
Ã
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
––– –––
1.3
V
–––
72
–––
ns
–––
81
–––
––– 210 –––
nC
T
J
= 125°C
––– 268 –––
–––
5.3
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 106A, V
GS
= 0V
T
J
= 25°C
V
R
= 85V,
T
J
= 125°C
I
F
= 106A
di/dt = 100A/μs
T
J
= 25°C
f
f
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.057mH
R
G
= 25Ω, I
AS
= 106A, V
GS
=10V. Part not recommended for use
above this value .
I
SD
≤
106A, di/dt
≤
1319A/μs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400μs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering echniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C
R
θJC
value shown is at time zero
2
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IRFS/SL4010PbF
1000
TOP
VGS
15V
10V
8.0V
7.0V
5.0V
4.5V
4.3V
4.0V
1000
TOP
VGS
15V
10V
8.0V
7.0V
5.0V
4.5V
4.3V
4.0V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
10
100
1
≤
60μs PULSE WIDTH
Tj = 25°C
0.1
0.1
4.0V
1
10
100
4.0V
10
0.1
1
≤
60μs PULSE WIDTH
Tj = 175°C
10
100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
Fig 2.
Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
ID = 106A
VGS = 10V
2.0
100
TJ = 175°C
10
T J = 25°C
1.5
1
VDS = 50V
≤60μs
PULSE WIDTH
2
3
4
5
6
7
1.0
0.1
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics
100000
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
Fig 4.
Normalized On-Resistance vs. Temperature
14.0
VGS, Gate-to-Source Voltage (V)
12.0
10.0
8.0
6.0
4.0
2.0
0.0
ID= 106A
C, Capacitance (pF)
VDS= 80V
VDS= 50V
10000
Ciss
1000
Coss
Crss
100
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
0
25
50
75 100 125 150 175 200 225
QG, Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFS/SL4010PbF
1000
10000
1000
100
10
1
0.1
0.01
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
10
10msec
100μsec
1msec
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100
T J = 175°C
10
T J = 25°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
DC
VGS = 0V
1.0
0.2
0.6
1.0
1.4
1.8
VSD, Source-to-Drain Voltage (V)
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
200
180
160
ID, Drain Current (A)
Fig 8.
Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
130
Id = 5mA
125
120
115
110
105
100
95
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
140
120
100
80
60
40
20
0
25
50
75
100
125
150
175
T C , Case Temperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
4.0
3.5
3.0
Fig 10.
Drain-to-Source Breakdown Voltage
1400
EAS , Single Pulse Avalanche Energy (mJ)
1200
1000
800
600
400
200
0
ID
TOP
12.5A
17A
BOTTOM 106A
Energy (μJ)
2.5
2.0
1.5
1.0
0.5
0.0
0
20
40
60
80
100
120
25
50
75
100
125
150
175
Fig 11.
Typical C
OSS
Stored Energy
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (°C)
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
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IRFS/SL4010PbF
1
Thermal Response ( Z thJC ) °C/W
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
τ
C
τ
1
τ
2
τ
τ
J
Ri (°C/W)
0.17537
0.22547
τi
(sec)
0.000343
0.006073
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Ci=
τi/Ri
Ci i/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.01
0.1
0.0001
1E-006
1E-005
0.0001
0.001
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01
0.05
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔTj
= 150°C and
Tstart =25°C (Single Pulse)
10
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
ΔΤ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
tav (sec)
1.0E-03
1.0E-02
1.0E-01
Fig 14.
Typical Avalanche Current vs.Pulsewidth
350
300
EAR , Avalanche Energy (mJ)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 106A
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
ΔT
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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5
