without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
12/19/05
1
IS41C16257
IS41LV16257
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
ISSI
CAS
WE
®
OE
RAS
RAS
CLOCK
GENERATOR
DATA I/O BUS
REFRESH
COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS
SENSE AMPLIFIERS
I/O0-I/O15
MEMORY ARRAY
262,144 x 16
ADDRESS
BUFFERS
A0-A8
PIN CONFIGURATIONS
40-Pin TSOP (Type II)
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
40
39
38
37
36
35
34
33
32
31
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
PIN DESCRIPTIONS
40-Pin SOJ
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
A0-A8
I/O0-I/O15
WE
OE
RAS
UCAS
LCAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Upper Column Address
Strobe
Lower Column Address
Strobe
Power
Ground
No Connection
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
12/19/05
IS41C16257
IS41LV16257
TRUTH TABLE
Function
Standby
Read: Word
Read: Lower Byte
Read: Upper Byte
Write: Word (Early Write)
Write: Lower Byte (Early Write)
Write: Upper Byte (Early Write)
Read-Write
(1,2)
Hidden Refresh
2)
RAS-Only
Refresh
CBR Refresh
(3)
RAS
H
L
L
L
L
L
L
L
Read L∅H∅L
Write L∅H∅L
L
H∅L
LCAS
H
L
L
H
L
L
H
L
L
L
H
L
UCAS
H
L
H
L
L
H
L
L
L
L
H
L
WE
X
H
H
H
L
L
L
H∅L
H
L
X
X
OE
X
L
L
L
X
X
X
L∅H
L
X
X
X
Address t
R
/t
C
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/COL
ROW/NA
X
ISSI
I/O
High-Z
D
OUT
Lower Byte, D
OUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, D
OUT
D
IN
Lower Byte, D
IN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, D
IN
D
OUT
, D
IN
D
OUT
D
OUT
High-Z
High-Z
®
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either
LCAS
or
UCAS
active).
2. These READ cycles may also be BYTE READ cycles (either
LCAS
or
UCAS
active).
3. At least one of the two CAS signals must be active (LCAS or
UCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
12/19/05
3
IS41C16257
IS41LV16257
FUNCTIONAL DESCRIPTION
The IS41C16257 and the IS41LV16257 are CMOS DRAMs
optimized for high-speed bandwidth, low-power applications.
During READ or WRITE cycles, each bit is uniquely
addressed through the 18 address bits. These are entered
nine bits (A0-A8) at a time. The row address is latched by
the Row Address Strobe (RAS). The column address is
latched by the Column Address Strobe (CAS).
RAS
is used
to latch the first nine bits and
CAS
is used to latch the latter
nine bits.
The IS41C16257 and the IS41LV16257 has two
CAS
controls,
LCAS
and
UCAS.
The
LCAS
and
UCAS
inputs
internally generate a
CAS
signal functioning in an identical
manner to the single
CAS
input on the other 256K x 16
DRAMs. The key difference is that each
CAS
controls its
corresponding I/O tristate logic (in conjunction with
OE
and
WE
and
RAS). LCAS
controls
I/O0 - I/O7 and
UCAS
controls I/O8 - I/O15.
The IS41C16257 and the IS41LV16257
CAS
function is
determined by the first
CAS
(LCAS or
UCAS)
transitioning
LOW and the last transitioning back HIGH. The two
CAS
controls give the IS41C16257 both BYTE READ and BYTE
WRITE cycle capabilities.
ISSI
on the timing relationships between these parameters.
®
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid at or
before the falling edge of
CAS
or
WE,
whichever occurs last.
Refresh Cycle
To retain data, 512 refresh cycles are required in each
8 ms period. There are two ways to refresh the memory:
1. By clocking each of the 512 row addresses (A0 through
A8) with
RAS
at least once every 8 ms. Any read, write,
read-modify-write or
RAS-only
cycle refreshes the ad-
dressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while
holding
CAS
LOW. In
CAS-before-RAS
refresh cycle, an
internal 9-bit counter provides the row addresses and the
external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data access
or device selection is allowed. Thus, the output remains in
the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bringing
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensure proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum t
RAS
time has expired. A new cycle
must not be initiated until the minimum precharge time t
RP
,
t
CP
has elapsed.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initialization
cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with V
CC
or be held at a valid V
IH
to avoid current surges.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The column
address must be held for a minimum time specified by t
AR
.
Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is dependent
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
12/19/05
IS41C16257
IS41LV16257
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Operation Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
–1.0 to +7.0
–0.5 t0 +4.6
–1.0 to +7.0
–0.5 t0 +4.6
50
1
0 to 70
–40 to +85
–55 to +125
Unit
V
V
mA
W
°C
°C
ISSI
®
Com.
Ind.
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND)
Symbol
V
CC
V
CC
V
IH
V
IH
V
IL
V
IL
T
A
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input High Voltage
Input Low Voltage
Input Low Voltage
Ambient Temperature
Voltage
5V
3.3V
5V
3.3V
5V
3.3
Com.
Ind.
Min.
4.5
3.0
2.4
2.0
–1.0
–0.3
0
–40
Typ.
5.0
3.3
—
—
—
—
—
—
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
85
Unit
V
V
V
V
V
V
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A8
Input Capacitance:
RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
5
7
7
Unit
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, V
CC
= 5.0V + 10% or Vcc=3.3V ± 10%.
Integrated Silicon Solution, Inc. — 1-800-379-4774
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