IS43/46R83200F
IS43/46R16160F
IS43/46R32800F
8Mx32, 16Mx16, 32Mx8
256Mb DDR SDRAM
FEATURES
• VDD and VDDQ: 2.5V ± 0.2V
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers
per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
• DQS is edge-aligned with data for READs and
centre-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data Mask for write data. DM masks write data
at both rising and falling edges of data strobe
• Burst Length: 2, 4 and 8
• Burst Type: Sequential and Interleave mode
• Programmable CAS latency: 2, 2.5 and 3
• Auto Refresh and Self Refresh Modes
• Auto Precharge
• T
RAS
Lockout supported (t
RAP
= t
RCD
)
OCTOBER 2016
DEVICE OVERVIEW
ISSI’s 256-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 268,435,456-bit memory
array is internally organized as four banks of 64Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 8-bit, 16-bit and 32-bit data word size
Input data is registered on the I/O pins on both edges
of Data Strobe signal(s), while output data is referenced
to both edges of Data Strobe and both edges of CLK.
Commands are registered on the positive edges of CLK.
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.
ADDRESS TABLE
Parameter
Configuration
8M x 32
2M x 32 x 4
banks
16M x 16
4M x 16 x 4
banks
BA0, BA1
A10/AP
32M x 8
8M x 8 x 4
banks
BA0, BA1
A10/AP
Bank Address BA0, BA1
Pins
Autoprecharge A8/AP
Pins
Row Address
Column
Address
4K(A0 – A11)
512(A0 – A7,
A9)
8K(A0 – A12) 8K(A0 – A12)
512(A0 – A8)
1K(A0 – A9)
OPTIONS
• Configuration(s): 8Mx32, 16Mx16, 32Mx8
• Package(s):
144 Ball BGA (x32)
66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16)
• Lead-free package available
• Temperature Range:
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Automotive, A1 (-40°C to +85°C)
Automotive, A2 (-40°C to +105°C)
Refresh Count
Com./Ind./A1
4K / 64ms
A2
4K / 16ms
8K / 64ms
8K / 16ms
8K / 64ms
KEY TIMING PARAMETERS
Speed Grade
F
Ck
Max CL = 3
F
Ck
Max CL = 2.5
F
Ck
Max CL = 2
-5
200
167
133
-6
167
167
133
Units
MHz
MHz
MHz
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. B
10/18/2016
1
IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
FUNCTIONAL BLOCK DIAGRAM (
x
32)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
Mode Registers and
Ext. Mode Registers
DATA IN
BUFFER
32
32
4
DM0-DM3
REFRESH
CONTROLLER
I/O 0-31
4
DQS0-DQS3
SELF
REFRESH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
14
CONTROLLER
32
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
32
REFRESH
COUNTER
2
4096
4096
4096
4096
12
ROW DECODER
MULTIPLEXER
12
MEMORY CELL
ARRAY
12
ROW
ADDRESS
LATCH
12
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
2
COLUMN
ADDRESS LATCH
9
512
(x 32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
9
2
Integrated Silicon Solution, Inc.
Rev. B
10/18/2016
IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
FUNCTIONAL BLOCK DIAGRAM (
x
16)
CK
CK
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
&
CLOCK
GENERATOR
Mode Registers and
Ext. Mode Registers
DATA IN
BUFFER
16
16
2
LDM, UDM
REFRESH
CONTROLLER
I/O 0-15
2
LDQS, UDQS
SELF
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
REFRESH
15
CONTROLLER
16
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
16
REFRESH
COUNTER
2
8192
8192
8192
8192
13
ROW DECODER
MULTIPLEXER
13
MEMORY CELL
ARRAY
13
ROW
ADDRESS
LATCH
13
13
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
2
COLUMN
ADDRESS LATCH
9
512
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
9
Integrated Silicon Solution, Inc.
Rev. B
10/18/2016
3
IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
PIN CONFIGURATIONS
66 pin TSOP - Type II for x8
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
NC
V
DDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
PIN DESCRIPTION: x8
A0-A12
A0-A9
BA0, BA1
DQ0 – DQ7
CK, CK
CKE
CS
CAS
RAS
WE
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe
Command
Row Address Strobe
Command
Write Enable
DM
DQS
VDD
VDDQ
VSS
VSSQ
VREF
NC
Data Write Mask
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
4
Integrated Silicon Solution, Inc.
Rev. B
10/18/2016
IS43/46R83200F
IS43/46R16160F, IS43/46R32800F
PIN CONFIGURATION
Package Code B: 60-ball FBGA (top view) for x8
(8mm x 13mm Body, 0.8mm Ball Pitch)
Top View
(Balls seen through the Package)
: Ball Existing
: Depopulated Ball
Top View(See the balls through the Package)
1 2 3
4 5 6
7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CK
A12
A11
A8
A6
A4
3
VSS
DQ6
DQ5
DQ4
DQS
DM
CK
CKE
A9
A7
A5
VSS
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ1
DQ2
DQ3
NC
NC
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
BGA Package Ball Pattern
Top View
x 8 Device Ball Pattern
PIN DESCRIPTION: x8
A0-A12
A0-A9
BA0, BA1
DQ0 – DQ7
CK, CK
CKE
CS
CAS
RAS
WE
DM
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Column Address Strobe
Command
Row Address Strobe Command
Write Enable
Data Write Mask
DQS
VDD
VDDQ
VSS
VSSQ
VREF
NC
Data Strobe
Power
Power Supply for I/O Pins
Ground
Ground for I/O Pins
SSTL_2 reference voltage
No Connection
Integrated Silicon Solution, Inc.
Rev. B
10/18/2016
5
