notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
01/14/09
1
IS43R32800
FUNCTIONAL BLOCK DIAGRAM
DQ 0 - 31
DQS0 - 3
DLL
I/O Buffer
DQ S B uffer
Memory
Array
Ba nk #0
Memory
Array
Ba nk #1
Memory
Array
Ba nk #2
Memory
Array
Ba nk #3
Mode Re gister
Control C ircu itry
Addres s B uffer
Cl ock B uffer
A0-1 1
BA 0,1
CLK
/CLK
CKE
Control Signal B uffer
/CS /RAS /CAS
/WE
D M0- 3
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev.
A
01/14/09
IS43R32800
PIN CONFIGURATION
Package Code: B 144-ball FBGA (Top View) (12.00mm x 12.00mm Body, 0.8mm Ball Pitch
1
A
B
C
D
E
F
G
H
J
K
L
M
DQS0
DQ 4
DQ 6
DQ 7
DQ 17
DQ 19
DQS2
DQ 21
DQ 22
/CAS
/R AS
/CS
2
DM0
VDDQ
DQ 5
VDDQ
DQ 16
DQ 18
DM2
DQ 20
DQ 23
/W E
NC
NC
3
VSSQ
NC
VSSQ
VD D
VDDQ
VDDQ
NC
VDDQ
VDDQ
VD D
NC
BA 0
4
DQ 3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
BA 1
A0
5
DQ 2
DQ 1
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
A1 0
A2
A1
6
DQ 0
VDDQ
VD D
VSS
VSS
VSS
VSS
VSS
VSS
VD D
A1 1
A3
7
DQ 31
VDDQ
VD D
VSS
VSS
VSS
VSS
VSS
VSS
VD D
A9
A4
8
DQ 29
DQ 30
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
NC
A5
A6
9
DQ 28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC
A7
10
VSSQ
NC
VSSQ
VD D
VDDQ
VDDQ
NC
VDDQ
VDDQ
VD D
CL K
A8 /AP
11
DM3
VDDQ
DQ 26
VDDQ
DQ 15
DQ 13
DM1
DQ 11
DQ 9
NC
/CLK
CK E
12
DQS3
DQ 27
DQ 25
DQ 24
DQ 14
DQ 12
DQS1
DQ 10
DQ 8
NC
NC
VREF
PIN DESCRIPTIONS
CLK, /CLK
CKE
/CS
/RAS
/CAS
/WE
DQ 0-31
DM 0-3
: Ma ster Cl ock
: Clock En able
: Ch ip Select
: Ro w Address Strobe
: Column A ddress Strobe
: Write Enab le
: Data I/O
: Write Mask
A0-11
BA 0,1
V
DD
V
DDQ
Vs s
VssQ
DQ S0-3
V
REF
: Address Inpu t
: Ba nk A ddress Inpu t
: Pow er Supply
: Power Supply for Output
: Ground
: Ground for Output
: Data Strobe
: Reference Voltage
Integrated Silicon Solution, Inc. — www.issi.com
Rev.
A
01/14/09
3
IS43R32800
PIN FUNCTIONS
SYMBOL
TYPE
DESCRIPTION
Cl ock: CL K a nd/CLK are differential clock inputs. A ll address and control
input signals are sampled on the crossing of the positive edge of CL K a nd
negative edgeof /CLK . Output (read) data is referenced to the crossings of
CL K a nd /CLK (both directions of crossing).
Cl ock E nable: CK E controls internal clock. W hen CKE is low, internal clock
for the following cycle is ceased. C KE is also used to select auto/ self refresh.
Af ter self refresh mode is started, CK E becomes asynchronous input. Self refresh
is maintained as long as CK E i s low.
Chip Select: W hen /CS is high, any command means No Operation.
Combination of /RA S, /CAS , /WE defines basic commands.
A0-1 1 specify the Row / Column Address in conjunction with BA0,1. T he
Row Address is specifi ed by A0-11. The Column Address is specified by
A0-7 ,A 9. A8 is also used to indicate precharge option. W hen A8 is
high at a read / write command, an auto precharge is performed. When A8
is high at a precharge command, all banks are precharged.
Bank Address: BA 0,1 specifies one of four banks to which a command is
applied. BA 0,1 must be set with ACT, PR E, READ, WR IT E commands.
Data Input/Output: D ata bus
Data Strobe: Outputwith read data, inputwith write data. E dge-aligned
with read data, centered in write data. Used to captu write data.
re
DQS 0 for DQ0 - DQ7, DQS 1 for DQ8 - DQ15, DQS2 for DQ16 - DQ23,
DQS3 for DQ24 - DQ31.
Input Data Mask: DM is an inputmask signal for write data. I nput data
is masked when DM is sampled HIG H along with that input data
during a WR IT E access. DM is sampled on both edges of D QS.
Al though DM pins are input only, the DM loading matches the DQ
andDQS loading. DM 0 for DQ0 - DQ7, DM1 for DQ8 - DQ15,
DM 2 for DQ16 - DQ23, DM 3 for DQ24 - DQ31.
Power Supp for the memory array and peripheral circuitry.
ly
V
DDQ
and Vss
Q
are supplied to the Output Buffers only.
SST L_ 2 reference voltage.
CL K, /CLK
Input
CK E
I nput
/CS
/RAS , /CAS, /WE
I nput
I nput
A0-1 1
Input
BA 0,1
DQ0-31
Input
Input / Output
DQS0- 3
Input / Output
DM0- 3
Input
V
DD
, Vs s
V
DDQ
, Vss
Q
Vref
Power Supp
ly
Power Supp
ly
Input
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev.
A
01/14/09
IS43R32800
FUNCTIONAL DESCRIPTION
ISSI's 256-Mbit DDR SDRAM provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge and auto / self refresh. E ach command is defined by control signals of /RA S, /CAS and
,
/WE at CLK rising edge. I n addition to 3 signals, /CS ,C KE and A8 are usedas chip select, refresh
option, and prechargeoption, respect
ively. To know the detailed definition of commands, please
see the command truth table.
/CLK
CL K
/CS
/RAS
/CAS
/WE
CK E
A8
Chip Select : L =select, H=deselect
Command
Command
Command
Refresh Option @ refresh command
Precharge Option @ precharge or read/write command
define basic commands
Activate ( ACT)
[/RA S =L, /CAS =/WE =H ]
AC T c ommand activates a row in an idle bank indicated by BA .
Read (R EAD)
[/RAS =H , /CA S =L, /WE = H]
RE AD command starts burst read from the active bank indicated by BA . F irst output data appear after
s
/CAS latency. When A8 =H at this command, the bank is deactivated after the burst read (auto-
precharge READ A )
Write (WRITE)
[/RA S =H, /CAS =/WE =L ]
WR IT E c ommand starts burst write to the active bank indicated by BA . T otal data length to be written
is set by burst length. W hen A8 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA )
Prechar ge (P RE )
[ /RAS =L , /CA S =H, /WE = L]
PR E c ommand deactivates the active bank indicated by BA . T his command also terminates burst read
/write operation. When A8 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Ref resh (REFA )
[ /RAS =/CA S =L, /WE = CK E = H]
RE FA command starts auto-refresh cycle. R efresh address including bank address are generated
internally. A fter this command, the banks are precharged automatically.
