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IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

128K x 32, 128K x 36, 256K x 18

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth ex-

pansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• Power Supply

LPS: V

3.3V + 5%,

ddq

3.3V/2.5V + 5%

VPS: V

2.5V + 5%,

ddq

2.5V + 5%

• JEDEC 100-Pin QFP, 119-ball and 165-ball

BGA packages

• Automotive temperature available

• Lead Free available

DECEMBER 2013

4 Mb SYNCHRONOUS PIPELINED, SINgLE CYCLE DESELECT STATIC RAM

DESCRIPTION

The

ISSI

IS61(64)LPS12832A, IS61(64)LPS/VP-

S12836A and IS61(64)LPS/VPS25618A are

high-speed,

low-power synchronous static

RAMs

designed to provide

burstable, high-performance memory for communication

and networking applications. The IS61(64)LPS12832A

organized as 131,072 words by 32 bits.

The IS61(64)LPS/

VPS12836A is organized as 131,072 words by 36 bits.

The IS61(64)LPS/VPS25618A

is organized as 262,144

words by 18 bits. Fabricated with

ISSI

's advanced CMOS

technology, the device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit. All synchronous inputs pass

through registers controlled by a positive-edge-triggered

single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (BWE) input combined with one or more

individual byte write signals (BWx).

In addition, Global

Write (GW)

is available for writing all bytes at one time,

regardless of the byte write controls.

Bursts can be initiated with either ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the

ADV

(burst address

advance) input pin.

The mode pin is used to select the burst sequence or-

der, Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH

or left floating.

FAST ACCESS TIME

Symbol

Parameter

Clock Access Time

Cycle Time

Frequency

250

2.6

250

200

3.1

200

Units

MHz

Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liabil-

ity arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

Rev. H1

12/06/2013

IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

BLOCK DIAGRAM

MODE

CLK

A0'

BINARY

COUNTER

ADV

ADSC

ADSP

CLR

A1'

128Kx32;

128Kx36;

256Kx18

MEMORY ARRAY

17/18

15/16

ADDRESS

CLK

32, 36,

or 18

32, 36,

or 18

BWE

BW(a-d)

x18: a,b

x32/x36: a-d

DQ(a-d)

BYTE WRITE

REGISTERS

CLK

CE2

2/4/8

ENABLE

CLK

INPUT

REGISTERS

CLK

OUTPUT

REGISTERS

CLK

32, 36,

or 18

DQa - DQd

POWER

DOWN

ENABLE

DELAY

CLK

Integrated Silicon Solution, Inc.

Rev. H1

12/06/2013

IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

165-PIN BgA

165-Ball, 13x15 mm BGA

1mm Ball Pitch, 11x15 Ball Array

119-PIN BgA

119-Ball, 14x22 mm BGA

1mm Ball Pitch, 7x17 Ball Array

BOTTOM VIEW

Integrated Silicon Solution, Inc.

Rev. H1

12/06/2013

IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

119 BGA PACKAGE PIN CONFIGURATION

128k

36 (TOP VIEW)

DDQ

DQc

DDQ

DQc

DDQ

DQd

DDQ

DQd

DDQ

CE2

DQPc

DQc

DQd

DQPd

Vss

BWc

Vss

BWd

Vss

MODE

ADSP

ADSC

ADV

CLK

BWE

Vss

BWb

Vss

BWa

Vss

CE2

DQPb

DQb

DQa

DQPa

DDQ

DQb

DDQ

DQb

DDQ

DQa

DDQ

DQa

DDQ

Note:

* A

and A

are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

A0, A1

ADV

ADSP

ADSC

CLK

CE, CE2, CE2

BWx (x=a-d)

BWE

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address

Advance

Address Status Processor

Address Status Controller

Global Write Enable

Synchronous Clock

Synchronous Chip Select

Synchronous Byte Write Controls

Byte Write Enable

Symbol

MODE

DQa-DQd

DQPa-Pd

ddq

Vss

Pin Name

Output Enable

Power Sleep Mode

Burst Sequence Selection

No Connect

Data Inputs/Outputs

Output Power Supply

Power Supply

Output Power Supply

Ground

Integrated Silicon Solution, Inc.

Rev. H1

12/06/2013

IS61(64)LPS12832A

IS61(64)LPS12836A IS61(64)VPS12836A

IS61(64)LPS25618A IS61(64)VPS25618A

119 BGA PACKAGE PIN CONFIGURATION

256k

18 (TOP VIEW)

VDDQ

DQb

VDDQ

DQb

VDDQ

DQb

VDDQ

DQb

VDDQ

CE2

DQb

VDD

DQb

DQPb

Vss

BWb

Vss

MODE

ADSP

ADSC

VDD

ADV

VDD

CLK

BWE

A1*

A0*

VDD

Vss

BWa

Vss

CE2

DQPa

DQa

VDD

DQa

VDDQ

DQa

VDDQ

DQa

VDDQ

DQa

VDDQ

DQa

VDDQ

Note:

* A

and A

are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

A0, A1

ADV

ADSP

ADSC

CLK

CE, CE2, CE2

BWx (x=a,b)

BWE

Pin Name

Address Inputs

Synchronous Burst Address Inputs

Synchronous Burst Address

Advance

Address Status Processor

Address Status Controller

Global Write Enable

Synchronous Clock

Synchronous Chip Select

Synchronous Byte Write Controls

Byte Write Enable

Symbol

MODE

DQa-DQb

DQPa-Pb

ddq

Vss

Pin Name

Output Enable

Power Sleep Mode

Burst Sequence Selection

No Connect

Data Inputs/Outputs

Output Power Supply

Power Supply

Output Power Supply

Ground

Integrated Silicon Solution, Inc.

Rev. H1

12/06/2013

参数对比

与IS61LPS25618A-200B2I相近的元器件有：IS61LPS12836A-200B2I、IS61LPS25618A-200TQI、IS61LPS25618A-200TQLI、IS61LPS12836A-200TQLI、IS61LPS12836A-200B2LI、IS61LPS12836A-200TQI。描述及对比如下：

型号	IS61LPS25618A-200B2I	IS61LPS12836A-200B2I	IS61LPS25618A-200TQI	IS61LPS25618A-200TQLI	IS61LPS12836A-200TQLI	IS61LPS12836A-200B2LI	IS61LPS12836A-200TQI
描述	Cache SRAM, 256KX18, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119	Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-119	256KX18 CACHE SRAM, 3.1ns, PQFP100, TQFP-100	Cache SRAM, 256KX18, 3.1ns, CMOS, PQFP100, LEAD FREE, TQFP-100	Cache SRAM, 128KX36, 3.1ns, CMOS, PQFP100, LEAD FREE, TQFP-100	Cache SRAM, 128KX36, 3.1ns, CMOS, PBGA119, 14 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-119	128KX36 CACHE SRAM, 3.1ns, PQFP100, TQFP-100
是否无铅	含铅	含铅	含铅	不含铅	不含铅	不含铅	含铅
是否Rohs认证	不符合	不符合	不符合	符合	符合	符合	不符合
零件包装代码	BGA	BGA	QFP	QFP	QFP	BGA	QFP
包装说明	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	TQFP-100	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	BGA, BGA119,7X17,50	TQFP-100
针数	119	119	100	100	100	119	100
Reach Compliance Code	compliant	compli	compliant	compliant	compliant	compliant	compli
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991	3A991.B.2.A	3A991.B.2.A
最长访问时间	3.1 ns	3.1 ns	3.1 ns	3.1 ns	3.1 ns	3.1 ns	3.1 ns
其他特性	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz	200 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PBGA-B119	R-PBGA-B119	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PBGA-B119	R-PQFP-G100
JESD-609代码	e0	e0	e0	e3	e3	e1	e0
长度	22 mm	22 mm	20 mm	20 mm	20 mm	22 mm	20 mm
内存密度	4718592 bit	4718592 bi	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bi
内存集成电路类型	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
内存宽度	18	36	18	18	36	36	36
湿度敏感等级	3	3	3	3	3	3	3
功能数量	1	1	1	1	1	1	1
端子数量	119	119	100	100	100	119	100
字数	262144 words	131072 words	262144 words	262144 words	131072 words	131072 words	131072 words
字数代码	256000	128000	256000	256000	128000	128000	128000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
组织	256KX18	128KX36	256KX18	256KX18	128KX36	128KX36	128KX36
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	BGA	LQFP	LQFP	LQFP	BGA	LQFP
封装等效代码	BGA119,7X17,50	BGA119,7X17,50	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	BGA119,7X17,50	QFP100,.63X.87
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY	GRID ARRAY	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	GRID ARRAY	FLATPACK, LOW PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	260	260	260	NOT SPECIFIED
电源	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2.41 mm	2.41 mm	1.6 mm	1.6 mm	1.6 mm	2.41 mm	1.6 mm
最大待机电流	0.000075 A	0.075 A	0.000075 A	0.000075 A	0.075 A	0.075 A	0.075 A
最小待机电流	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
最大压摆率	0.21 mA	0.21 mA	0.21 mA	0.21 mA	0.21 mA	0.21 mA	0.21 mA
最大供电电压 (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V	3.465 V
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)
端子形式	BALL	BALL	GULL WING	GULL WING	GULL WING	BALL	GULL WING
端子节距	1.27 mm	1.27 mm	0.65 mm	0.65 mm	0.65 mm	1.27 mm	0.65 mm
端子位置	BOTTOM	BOTTOM	QUAD	QUAD	QUAD	BOTTOM	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	40	10	40	NOT SPECIFIED
宽度	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
厂商名称	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
Factory Lead Time	10 weeks	10 weeks	12 weeks	10 weeks	-	10 weeks	12 weeks
Base Number Matches	1	1	1	1	1	-	-