DATASHEET
ISL5961
14-Bit, +3.3V, 130/210+MSPS, High Speed D/A Converter
The ISL5961 is a 14-bit, 130/210+MSPS (Mega Samples
Per Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in high
performance communication systems such as base
transceiver stations utilizing 2.5G or 3G cellular protocols.
This device complements the ISL5x61 family of high speed
converters, which include 10, 12, and 14-bit devices.
FN6007
Rev 4.00
Oct 7, 2015
Features
• Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS
• Low Power . . . . . 103mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(75dBc to Nyquist, f
S
= 130MSPS, f
OUT
= 10MHz)
Ordering Information
PART
NUMBER
ISL5961IBZ
(No
longer available,
recommended
replacement:
ISL5961IAZ)
(See Note)
ISL5961IAZ
(See Note)
ISL5961/2IBZ
(See Note)
(No
longer available,
recommended
replacement:
ISL5961/2IAZ)
ISL5961/2IAZ
(See Note)
ISL5961EVAL1
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
M28.3
CLOCK
SPEED
130MHz
• UMTS Adjacent Channel Power =71dB at 19.2MHz
• EDGE/GSM SFDR = 94dBc at 11MHz in 20MHz Window
• Pin compatible, 3.3V, Lower Power Replacement For The
AD9754 and HI5960
• Pb-free available
-40 to 85 28 Ld SOIC
(Pb-free)
-40 to 85 28 Ld TSSOP M28.173 130MHz
(Pb-free)
-40 to 85 28 Ld SOIC
(Pb-free)
M28.3
210MHz
Applications
• Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS-
95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
• BWA Infrastructure
• Medical/Test Instrumentation
• Wireless Communication Systems
-40 to 85 28 Ld TSSOP M28.173 210MHz
(Pb-free)
25
SOIC Evaluation Platform 210MHz
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL5961
TOP VIEW
D13 (MSB) 1
D12 2
D11
3
28 CLK
27 DV
DD
26 DCOM
25 NC
24 AV
DD
23 COMP
22 IOUTA
21 IOUTB
20 ACOM
19 NC
18 FSADJ
17 REFIO
16 REFLO
15 SLEEP
D10 4
D9 5
D8 6
D7 7
D6 8
D5 9
D4 10
D3 11
D2 12
D1 13
D0 (LSB) 14
FN6007 Rev 4.00
Oct 7, 2015
Page 1 of 14
ISL5961
Typical Applications Circuit
ISL5961
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13 (1)
D12 (2)
D11 (3)
D10 (4)
D9 (5)
D8 (6)
D7 (7)
D6 (8)
D5 (9)
D4 (10)
D3 (11)
D2 (12)
D1 (13)
D0 (LSB) (14)
CLK (28)
50
BEAD
+
10F
10H
0.1F
DCOM (26)
DV
DD
(27)
(20) ACOM
(24) AV
DD
(23) COMP
0.1F
FERRITE
BEAD
10H
0.1F
10F
+
+3.3V (V
DD
)
1:1, Z1:Z2
(22) IOUTA
(21) IOUTB
50
(18) FSADJ
R
SET
(50)
REPRESENTS
ANY 50 LOAD
1.91k
(25, 19) NC
(15) SLEEP
(16) REFLO
(17) REFIO
0.1F
ONE CONNECTION
DCOM
ACOM
Functional Block Diagram
IOUTA
IOUTB
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
INPUT
LATCH
SWITCH
MATRIX
40
CASCODE
CURRENT
SOURCE
40
9 LSBs
+
31 MSB
SEGMENTS
D10
D11
D12
(MSB) D13
UPPER
5-BIT
DECODER
COMP
CLK
INT/EXT
VOLTAGE
REFERENCE
BIAS
GENERATION
REFLO REFIO
FSADJ
SLEEP
FN6007 Rev 4.00
Oct 7, 2015
Page 2 of 14
ISL5961
Pin Descriptions
PIN NO.
1-14
15
16
17
18
19, 25
21
22
23
24
20
26
27
28
PIN NAME
D13 (MSB) Through
D0 (LSB)
SLEEP
REFLO
REFIO
FSADJ
NC
IOUTB
IOUTA
COMP
AV
DD
ACOM
DCOM
DV
DD
CLK
DESCRIPTION
Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin
has internal 20A active pulldown current.
Connect to analog ground to enable internal 1.2V reference or connect to AV
DD
to disable internal reference.
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.F cap to ground when internal reference is enabled.
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current = 32 x V
FSADJ
/R
SET
.
No Connect. These should be grounded, but can be left disconnected.
The complementary current output of the device. Full scale output current is achieved when all input bits are
set to binary 0.
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
Connect 0.1F capacitor to ACOM.
Analog Supply (+2.7V to +3.6V).
Connect to Analog Ground.
Connect to Digital Ground.
Digital Supply (+2.7V to +3.6V).
Clock Input.
FN6007 Rev 4.00
Oct 7, 2015
Page 3 of 14
ISL5961
Absolute Maximum Ratings
Digital Supply Voltage DV
DD
to DCOM . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AV
DD
to ACOM. . . . . . . . . . . . . . . . . . +3.6V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DV
DD
+ 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV
DD
+ 0.3V
Analog Output Current (I
OUT
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Offset Drift Coefficient
Full Scale Gain Error, FSE
AV
DD
= DV
DD
= +3.3V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
T
A
= -40
o
C TO 85
o
C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
14
“Best Fit” Straight Line (Note 7)
(Note 7)
IOUTA (Note 7)
(Note 7)
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
-5
-3
-0.006
-
-3
-3
-
-
2
(Note 3)
-1.0
-
2.5
1.5
-
+5
+3
+0.006
Bits
LSB
LSB
% FSR
ppm
FSR/
o
C
% FSR
% FSR
ppm
FSR/
o
C
ppm
FSR/
o
C
mA
V
0.1
0.5
0.5
50
100
-
-
-
+3
+3
-
-
20
1.25
Full Scale Gain Drift
With External Reference (Note 7)
With Internal Reference (Note 7)
Full Scale Output Current, I
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
Maximum Clock Rate, f
CLK
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
IOUTFS = 20mA
IOUTFS = 2mA
AC CHARACTERISTICS
(Using Figure 13 with R
DIFF
= 50 and R
LOAD
= 50, Full Scale Output = -2.5dBm
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 210MSPS, f
OUT
= 80.8MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 210MSPS, f
OUT
= 40.4MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 20.2MHz, 20MHz Span (Notes 4, 7)
ISL5961/2IA, ISL5961/2IB
ISL5961IA, ISL5961IB
Full Scale Step
Full Scale Step
210
130
-
-
-
-
-
250
150
1.5
1.5
10
50
30
-
-
-
-
-
-
-
MHz
MHz
ns
ns
pF
pA/Hz
pA/Hz
-
-
-
73
82
86
-
-
-
dBc
dBc
dBc
FN6007 Rev 4.00
Oct 7, 2015
Page 4 of 14
ISL5961
Electrical Specifications
PARAMETER
Spurious Free Dynamic Range,
SFDR to Nyquist (f
CLK
/2)
AV
DD
= DV
DD
= +3.3V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
(Continued)
T
A
= -40
o
C TO 85
o
C
TEST CONDITIONS
f
CLK
= 210MSPS, f
OUT
= 80.8MHz (Notes 4, 7)
f
CLK
= 210MSPS, f
OUT
= 40.4MHz (Notes 4, 7, 9)
f
CLK
= 200MSPS, f
OUT
= 20.2MHz, T = 25
o
C (Notes 4, 7)
f
CLK
= 200MSPS, f
OUT
= 20.2MHz, T = -40
o
C to 85
o
C (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 50.5MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 40.4MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 10.1MHz (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 5.05MHz, T = 25
o
C (Notes 4, 7)
f
CLK
= 130MSPS, f
OUT
= 5.05MHz, T = -40
o
C to 85
o
C (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 40.4MHz (Notes 4, 7)
f
CLK
= 80MSPS, f
OUT
= 30.3MHz (Notes 4, 7)
f
CLK
= 80MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
f
CLK
= 80MSPS, f
OUT
= 10.1MHz (Notes 4, 7, 9)
f
CLK
= 80MSPS, f
OUT
= 5.05MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 20.2MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 10.1MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.05MHz (Notes 4, 7)
Spurious Free Dynamic Range,
SFDR in a Window with Eight Tones
f
CLK
= 210MSPS, f
OUT
= 28.3MHz to 45.2MHz, 2.1MHz Spacing,
50MHz Span (Notes 4, 7, 9)
f
CLK
= 130MSPS, f
OUT
=17.5MHz to 27.9MHz, 1.3MHz Spacing,
35MHz Span (Notes 4, 7)
f
CLK
= 80MSPS, f
OUT
= 10.8MHz to 17.2MHz, 811kHz Spacing,
15MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 4, 7)
Spurious Free Dynamic Range,
f
CLK
= 78MSPS, f
OUT
= 11MHz, in a 20MHz Window, RBW=30kHz
SFDR in a Window with EDGE or GSM (Notes 4, 7, 9)
Adjacent Channel Power Ratio,
ACPR with UMTS
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
Reference Input Impedance
Reference Input Multiplying Bandwidth (Note 7)
DIGITAL INPUTS
D13-D0, CLK
(Note 3)
(Note 3)
2.3
-
-25
3.3
0
-
-
1.0
+25
V
V
A
Reference is not intended to be externally loaded
Pin 18 Voltage with Internal Reference
1.2
-
-
-
-
1.23
40
0
1
1.0
1.3
-
-
-
-
V
ppm/
o
C
A
M
MHz
f
CLK
= 76.8MSPS, f
OUT
= 19.2MHz, RBW=30kHz (Notes 4, 7, 9)
MIN
-
-
62
60
-
-
-
-
72
70
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
52
61
64
-
59
63
70
75
79
-
61
65
71
71
78
70
75
79
67
70
77
78
94
71
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
Input Logic High Voltage with
3.3V Supply, V
IH
Input Logic Low Voltage with
3.3V Supply, V
IL
Sleep Input Current, I
IH
FN6007 Rev 4.00
Oct 7, 2015
Page 5 of 14
