ITS4100S-SJ-N
Smart High-Side NMOS-Power Switch
Data Sheet
Rev 1.0, 2012-09-01
Standard Power
Smart High-Side NMOS-Power Switch
ITS4100S-SJ-N
1
Features
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Overview
CMOS compatible input
Switching all types of resistive, inductive and capacitive loads
Fast demagnetization of inductive loads
Very low standby current
Optimized Electromagnetic Compatibility (EMC)
Overload protection
Current limitation
Short circuit protection
Thermal shutdown with restart
Overvoltage protection (including load dump)
Reverse battery protection with external resistor
Loss of GND and loss of Vbb protection
Electrostatic Discharge Protection (ESD)
Green Product (RoHS compliant)
PG-DSO-8
ITS4100S-SJ-N is not qualified and manufactured according to the requirements of Infineon Technologies with
regards to automotive and/or transportation applications.
Description
The ITS4100S-SJ-N is a protected single channel Smart High-Side NMOS-Power Switch in a PG-DSO-8 package
with charge pump and CMOS compatible input. The device is monolithically integrated in Smart technology.
Product Summary
Overvoltage protection
V
SAZmin
= 41V
Operating voltage range: 5V <
V
S
< 34V
On-state resistance
R
DSON
= typ 70mΩ
Nominal load current
I
LNOM
= 2A
Operating Temperature range: T
j
= -40°C to 125°C
Standby Current:
I
SSTB
= 15µA
Application
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All types of resistive, inductive and capacitive loads
Power switch for 12V and 24V DC applications with CMOS compatible control interface
Driver for electromagnetic relays
Power managment for high-side-switching with low current consumption in OFF-mode
Type
ITS4100S-SJ-N
Data Sheet
Package
PG-DSO-8
2
Marking
I100SN
Rev 1.0, 2012-09-01
ITS4100S-SJ-N
Block Diagram and Terms
2
Block Diagram and Terms
ITS4100S-SJ-N
5
6
Bias
Supervision
Overvoltage
Protection
Current
Limiter
VS
7
8
IN
2
ESD
Protection
Logic
Gate
Control
Circuit
NC
4
Temperature
Sensor
3
OUT
1
GND
Figure 1
Block diagram
Voltage- and Current-Definitions:
Switching Times and Slew Rate Definitions:
V
IN
H
L
I
S
ITS4100S-SJ-N
5
6
Bias
Supervision
Overvoltage
Protection
Current
Limiter
VS
V
OUT
t
+V
S
90%
70%
7
V
DS
V
FD S
8
IN
Gate
Control
Circuit
SR
OFF
40%
30%
I
IN
NC
2
ESD
Protection
Logic
SR
ON
10%
Temperature
Sensor
4
3
OUT
0
t
ON
t
OFF
t
V
S
I
OUT
V
O UT
I
L
R
L
V
IN
I
L
0
OFF
ON
OFF
V
ST
1
GND
t
GND
Figure 2
Data Sheet
Terms - parameter definition
3
Rev 1.0, 2012-09-01
ITS4100S-SJ-N
Pin Configuration
3
3.1
Pin Configuration
Pin Assignment
GND
1
8
VS
IN
2
7
VS
OUT
3
P-DSO-8
6
VS
NC
4
5
VS
Figure 3
Pin configuration top view, PG-DSO-8
3.2
Pin Definitions and Functions
Pin
1
2
3
4
5, 6, 7, 8
Symbol
GND
IN
OUT
NC
VS
Function
Logic ground
Input, controles the power switch; the powerswitch is ON when high
Output to the load
Not connected
Supply voltage (design the wiring for the maximum short circuit current and also
for low thermal resistance)
Data Sheet
4
Rev 1.0, 2012-09-01
ITS4100S-SJ-N
General Product Characteristics
4
4.1
General Product Characteristics
Absolute Maximum Ratings
Table 1
Parameter
Absolute maximum ratings
1)
at
T
j
= 25°C unless otherwise specified. Currents flowing into the
device unless otherwise specified in chapter “Block Diagram and Terms”
Symbol
Min.
Values
Typ.
Max.
40
V
V
-40°C <
T
j
< 150°C
Unit
Note /
Test Condition
Number
Supply voltage VS
Voltage
Voltage for short circuit protection
Output stage OUT
Output Current; (Short circuit
current see electrical
characteristics)
Input IN
Voltage
Current
Temperatures
Junction Temperature
Storage Temperature
Power dissipation
Ta = 25 °C
2)
Tj = 125 °C;
V
S
=13.5V;
I
L
= 1A
3)
ESD Susceptibility
ESD susceptibility (input pin)
ESD susceptibility (all other pins)
-5
1)
Not subject to production test, specified by design
V
S
V
SSC
I
OUT
4.1.1
4.1.2
4.1.3
V
S
self
A
limited
V
IN
I
IN
T
j
T
stg
P
tot
E
AS
V
ESD
V
ESD
-10
-5
-40
-55
16
5
125
125
1.5
870
V
mA
°C
°C
W
mJ
kV
kV
single pulse
HBM
4)
HBM
4)
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
Inductive load switch-off energy dissipation
-1
1
5
2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6 cm2 (one layer, 70mm thick) copper area for Vbb connection. PCB
is vertical without blown air
3) Not subject to production test, specified by design
4) ESD susceptibility HBM according to EIA/JESD 22-A 114.
Note: Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” the normal operating range. Protection functions
are neither designed for continuous nor repetitive operation.
Data Sheet
5
Rev 1.0, 2012-09-01
