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JANSR2N7397

Power Field-Effect Transistor, 4A I(D), 250V, 0.61ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, HERMETIC SEALED, METAL CAN-3

器件类别:分立半导体    晶体管   

厂商名称:Fairchild

厂商官网:http://www.fairchildsemi.com/

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器件参数
参数名称
属性值
厂商名称
Fairchild
零件包装代码
BCY
包装说明
CYLINDRICAL, O-MBCY-W3
针数
4
Reach Compliance Code
unknown
ECCN代码
EAR99
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
250 V
最大漏极电流 (ID)
4 A
最大漏源导通电阻
0.61 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码
TO-205AF
JESD-30 代码
O-MBCY-W3
元件数量
1
端子数量
3
工作模式
ENHANCEMENT MODE
封装主体材料
METAL
封装形状
ROUND
封装形式
CYLINDRICAL
极性/信道类型
N-CHANNEL
最大脉冲漏极电流 (IDM)
12 A
认证状态
Not Qualified
参考标准
MIL-19500/631
表面贴装
NO
端子形式
WIRE
端子位置
BOTTOM
晶体管应用
SWITCHING
晶体管元件材料
SILICON
文档预览
JANSR2N7397
Formerly FSL234R4
June 1998
4A, 250V, 0.610 Ohm, Rad Hard,
N-Channel Power MOSFET
Description
The Discrete Products Operation of Intersil Corporation has
developed a series of Radiation Hardened MOSFETs specif-
ically designed for commercial and military space applica-
tions. Enhanced Power MOSFET immunity to Single Event
Effects (SEE), Single Event Gate Rupture (SEGR) in particu-
lar, is combined with 100K RADS of total dose hardness to
provide devices which are ideally suited to harsh space envi-
ronments. The dose rate and neutron tolerance necessary
for military applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) struc-
ture. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications exposed
to radiation environments such as switching regulation,
switching converters, motor drives, relay drivers and drivers
for high-power bipolar switching transistors requiring high
speed and low gate drive power. This type can be operated
directly from integrated circuits.
BRAND
JANSR2N7397
[ /Title
(JANS
R2N73
97)
/Sub-
ject
(4A,
250V,
0.610
Ohm,
Rad
Hard,
N-
Chan-
nel
Power
MOS-
FET)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Semi-
con-
ductor,
4A,
250V,
0.610
Ohm,
Rad
Hard,
N-
Chan-
nel
Power
Features
• 4A, 250V, r
DS(ON)
= 0.610
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown and
V
GS
of 10V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 4.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
2
- Usable to 1E14 Neutrons/cm
2
Ordering Information
PART NUMBER
JANSR2N7397
PACKAGE
TO-205AF
Also available at other radiation and screening levels. See us
on the web, Intersil’s home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional
information.
Die Family TA17638.
MIL-PRF-19500/631.
Symbol
Package
TO-205AF
D
G
S
©2001 Fairchild Semiconductor Corporation
JANSR2N7397 Rev. A
JANSR2N7397
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
JANSR2N7397
250
250
4
2
12
±
20
25
10
0.20
12
4
12
-55 to 150
300
1.0
UNITS
V
V
A
A
A
V
W
W
W/
o
C
A
A
A
o
C
o
C
g
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
Drain to Gate Voltage (R
GS
= 20k
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100
µ
H, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
250
-
1.5
0.5
-
-
-
-
-
T
C
= 25
o
C
T
C
= 125
o
C
-
-
-
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 12V
V
GS
= 0V to 2V
V
DD
= 125V,
I
D
= 4A
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
0.460
-
-
-
-
-
-
32
-
5.8
15
-
-
MAX
-
5.0
4.0
-
25
250
100
200
2.56
0.610
1.110
60
140
120
95
60
40
2.3
8.4
20
5.0
175
UNITS
V
V
V
V
µ
A
µ
A
nA
nA
V
ns
ns
ns
ns
nC
nC
nC
nC
nC
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 200V,
V
GS
= 0V
V
GS
=
±
20V
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
Gate to Source Leakage Current
I
GSS
Drain to Source On-State Voltage
Drain to Source On Resistance
V
DS(ON)
r
DS(ON)12
V
GS
= 12V, I
D
= 4A
I
D
= 2A,
V
GS
= 12V
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge (Not on slash sheet)
Gate Charge at 12V
Threshold Gate Charge (Not on slash sheet)
Gate Charge Source
Gate Charge Drain
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
g(12)
Q
g(TH)
Q
gs
Q
gd
R
θ
JC
R
θ
JA
V
DD
= 125V, I
D
= 4A,
R
L
= 31.25
, V
GS
= 12V,
R
GS
= 7.5
©2001 Fairchild Semiconductor Corporation
JANSR2N7397 Rev. A
JANSR2N7397
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
SYMBOL
V
SD
t
rr
TEST CONDITIONS
I
SD
= 4A
I
SD
= 4A, dI
SD
/dt = 100A/
µ
s
MIN
0.6
-
TYP
-
-
MAX
1.8
400
UNITS
V
ns
Electrical Specifications up to 100K RAD
PARAMETER
Drain to Source Breakdown Volts (Note 3)
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±20V,
V
DS
= 0V
V
GS
= 0, V
DS
= 200V
V
GS
= 12V, I
D
= 4A
V
GS
= 12V, I
D
= 2A
MIN
250
1.5
-
-
-
-
MAX
-
4.0
100
25
2.56
0.610
UNITS
V
V
nA
µA
V
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
Single Event Effects (SEB, SEGR)
(Note 4)
ENVIRONMENT
(NOTE 5)
ION
SPECIES
Ni
Br
Br
Br
Br
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm
2
(typical), T = 25
o
C.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
TYPICAL LET
(MeV/mg/cm)
26
37
37
37
37
TYPICAL
RANGE (µ)
43
36
36
36
36
APPLIED
V
GS
BIAS
(V)
-20
-5
-10
-15
-20
(NOTE 6)
MAXIMUM
V
DS
BIAS
(V)
250
250
200
125
50
TEST
Single Event Effects Safe Operating
Area
SYMBOL
SEESOA
©2001 Fairchild Semiconductor Corporation
JANSR2N7397 Rev. A
JANSR2N7397
Typical Performance Curves
300
Unless Otherwise Specified
LET = 26MeV/mg/cm
2
, RANGE = 43
µ
LET = 37MeV/mg/cm
2
, RANGE = 36
µ
LIMITING INDUCTANCE (HENRY)
FLUENCE = 1E5 IONS/cm
2
(TYPICAL)
1E-3
1E-4
ILM = 10A
30A
1E-5
100A
300A
1E-6
200
V
DS
(V)
100
0
0
TEMP = 25
o
C
-5
-10
V
GS
(V)
-15
-20
-25
1E-7
10
30
100
DRAIN SUPPLY (V)
300
1000
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO I
AS
40
T
C
= 25
o
C
5
4
I
D
, DRAIN CURRENT (A)
I
D
, DRAIN (A)
10
100µs
3
2
1ms
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
0.1
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10ms
1
0
-50
100ms
700
0
50
100
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
2.5
PULSE DURATION = 250ms,V
GS
= 12V, I
D
= 2A
2.0
NORMALIZED r
DS(ON)
12V
Q
G
1.5
1.0
Q
GS
V
G
Q
GD
0.5
0.0
-80
CHARGE
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 5. BASIC GATE CHARGE WAVEFORM
FIGURE 6. NORMALIZED r
DS(ON)
vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
JANSR2N7397 Rev. A
JANSR2N7397
Typical Performance Curves
10
1
Unless Otherwise Specified
(Continued)
NORMALIZED THERMAL RESPONSE (Z
θ
JC
)
10
0
0.5
0.2
0.1
0.05
0.02
0.01
10
-2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
+ T
C
10
-4
10
-3
10
-2
10
-1
10
0
10
-1
P
DM
t
1
t
2
10
1
10
-3
10
-5
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
30
I
AS
, AVALANCHE CURRENT (A)
10
STARTING T
J
= 150
o
C
STARTING T
J
= 25
o
C
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R
0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
0.01
0.1
1
t
AV
, TIME IN AVALANCHE (ms)
10
1
0.001
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
20V
50Ω
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
©2001 Fairchild Semiconductor Corporation
JANSR2N7397 Rev. A
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器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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