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器件参数

参数名称

属性值

是否Rohs认证

不符合

零件包装代码

TSOP2

包装说明

TSOP2, TSOP54,.46,32

针数

Reach Compliance Code

unknow

ECCN代码

EAR99

Is Samacsys

访问模式

FOUR BANK PAGE BURST

最长访问时间

6 ns

其他特性

AUTO/SELF REFRESH

最大时钟频率 (fCLK)

100 MHz

I/O 类型

COMMON

交错的突发长度

1,2,4,8

JESD-30 代码

R-PDSO-G54

JESD-609代码

长度

22.22 mm

内存密度

134217728 bi

内存集成电路类型

SYNCHRONOUS DRAM

内存宽度

功能数量

端口数量

端子数量

字数

8388608 words

字数代码

8000000

工作模式

SYNCHRONOUS

最高工作温度

85 °C

最低工作温度

-40 °C

组织

8MX16

输出特性

3-STATE

封装主体材料

PLASTIC/EPOXY

封装代码

TSOP2

封装等效代码

TSOP54,.46,32

封装形状

RECTANGULAR

封装形式

SMALL OUTLINE, THIN PROFILE

峰值回流温度（摄氏度）

NOT SPECIFIED

电源

3.3 V

认证状态

Not Qualified

刷新周期

4096

座面最大高度

1.2 mm

自我刷新

YES

连续突发长度

1,2,4,8,FP

最大待机电流

0.001 A

最大压摆率

0.21 mA

最大供电电压 (Vsup)

3.6 V

最小供电电压 (Vsup)

3 V

标称供电电压 (Vsup)

3.3 V

表面贴装

YES

技术

CMOS

温度等级

INDUSTRIAL

端子面层

Tin/Lead (Sn/Pb)

端子形式

GULL WING

端子节距

0.8 mm

端子位置

DUAL

处于峰值回流温度下的最长时间

NOT SPECIFIED

宽度

10.16 mm

Base Number Matches

文档预览

K4S281632C-TI(P)

CMOS SDRAM

128Mbit SDRAM

2M x 16Bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.1

June 2001

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Jun. 2001

K4S281632C-TI(P)

Revision History

Revision 0.0 (November 18, 2000)

• First generation.

CMOS SDRAM

Revision 0.1 (June 20, 2001)

• Final Specification.

Rev. 0.1 Jun. 2001

K4S281632C-TI(P)

2M x 16Bit x 4 Banks Synchronous DRAM

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

•

Industrial Temperature Operation (- 40 to 85

°C)

CMOS SDRAM

GENERAL DESCRIPTION

The K4S281632C is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 2,097,152 words by 16

bits, fabricated with SAMSUNG′s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock I/O transactions are possible on

every clock cycle. Range of operating frequencies, programma-

ble burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

ORDERING INFORMATION

Part No.

K4S281632C-TI/P75

K4S281632C-TI/P1H

K4S281632C-TI/P1L

Max Freq.

133MHz(CL=3)

100MHz(CL=2)

100MHz(CL=3)

LVTTL

Interface Package

TSOP(II)

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

Data Input Register

LDQM

Bank Select

2M x 16

Refresh Counter

Output Buffer

Row Decoder

Sense AMP

Row Buffer

DQi

Address Register

CLK

ADD

Column Decoder

Col. Buffer

LRAS

LCBR

Latency & Burst Length

LCKE

LRAS

LCBR

LWE

LCAS

Programming Register

LWCBR

LDQM

Timing Register

CLK

CKE

RAS

CAS

LDQM

UDQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Jun. 2001

K4S281632C-TI(P)

PIN CONFIGURATION

(Top view)

DQ0

DDQ

DQ1

DQ2

SSQ

DQ3

DQ4

DDQ

DQ5

DQ6

SSQ

DQ7

LDQM

CAS

RAS

BA0

BA1

A10/AP

DQ15

SSQ

DQ14

DQ13

DDQ

DQ12

DQ11

SSQ

DQ10

DQ9

DDQ

DQ8

N.C/RFU

UDQM

CLK

CKE

N.C

A11

CMOS SDRAM

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

CLK

Name

System clock

Chip select

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.

Row address : RA

~ RA

, Column address : CA

~ CA

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when L(U)DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

This pin is recommended to be left No Connection on the device.

CKE

Clock enable

~ A

~ BA

RAS

CAS

L(U)DQM

D D

DDQ

SSQ

N.C/RFU

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Data output power/ground

No connection

/reserved for future use

Rev. 0.1 Jun. 2001

K4S281632C-TI(P)

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

I N

, V

OUT

, V

DDQ

S T G

Value

-1.0 ~ 4.6

-55 ~ +150

CMOS SDRAM

Unit

°C

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Recommended operating conditions (Voltage referenced to V

= 0V, T = -40 to 85

°C

)

Symbol

D D

, V

DDQ

I H

O H

Min

3.0

2.0

-0.3

2.4

-10

Typ

3.3

3.0

Max

3.6

+0.3

0.8

0.4

Unit

O H

= -2mA

= 2mA

Note

Notes :

1. V

I H

(max) = 5.6V AC.The overshoot voltage duration is

≤

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

Clock

= 3.3V, T

= 23°C, f = 1MHz, V

REF

=1.4V

200 mV)

Symbol

CLK

ADD

OUT

Min

2.5

4.0

Max

4.0

5.0

6.5

Unit

Note

RAS, CAS, WE, CS, CKE, DQM

Address

D Q

~ DQ

Notes :

1. -75 only specify a maximum value of 3.5pF

2. -75 only specify a maximum value of 3.8pF

3. -75 only specify a maximum value of 6.0pF

Rev. 0.1 Jun. 2001

参数对比

与K4S281632C-TP1L相近的元器件有：K4S281632C、K4S281632C-TI、K4S281632C-TI1H、K4S281632C-TI1L、K4S281632C-TI75、K4S281632C-TP、K4S281632C-TP1H、K4S281632C-TP75。描述及对比如下：

型号	K4S281632C-TP1L	K4S281632C	K4S281632C-TI	K4S281632C-TI1H	K4S281632C-TI1L	K4S281632C-TI75	K4S281632C-TP	K4S281632C-TP1H	K4S281632C-TP75
描述	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54	8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
内存宽度	16	16	16	16	16	16	16	16	16
功能数量	1	1	1	1	1	1	1	1	1
端子数量	54	54	54	54	54	54	54	54	54
组织	8MX16	8M × 16	8M × 16	8MX16	8MX16	8MX16	8M × 16	8MX16	8MX16
表面贴装	YES	Yes	Yes	YES	YES	YES	Yes	YES	YES
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子位置	DUAL	双	双	DUAL	DUAL	DUAL	双	DUAL	DUAL
是否Rohs认证	不符合	-	-	不符合	不符合	不符合	-	不符合	不符合
零件包装代码	TSOP2	-	-	TSOP2	TSOP2	TSOP2	-	TSOP2	TSOP2
包装说明	TSOP2, TSOP54,.46,32	-	-	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	-	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
针数	54	-	-	54	54	54	-	54	54
Reach Compliance Code	unknow	-	-	unknow	unknow	unknow	-	unknow	unknow
ECCN代码	EAR99	-	-	EAR99	EAR99	EAR99	-	EAR99	EAR99
Is Samacsys	N	-	-	N	N	N	-	N	N
访问模式	FOUR BANK PAGE BURST	-	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	6 ns	-	-	6 ns	6 ns	5.4 ns	-	6 ns	5.4 ns
其他特性	AUTO/SELF REFRESH	-	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	100 MHz	-	-	100 MHz	100 MHz	133 MHz	-	100 MHz	133 MHz
I/O 类型	COMMON	-	-	COMMON	COMMON	COMMON	-	COMMON	COMMON
交错的突发长度	1,2,4,8	-	-	1,2,4,8	1,2,4,8	1,2,4,8	-	1,2,4,8	1,2,4,8
JESD-30 代码	R-PDSO-G54	-	-	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	-	R-PDSO-G54	R-PDSO-G54
JESD-609代码	e0	-	-	e0	e0	e0	-	e0	e0
长度	22.22 mm	-	-	22.22 mm	22.22 mm	22.22 mm	-	22.22 mm	22.22 mm
内存密度	134217728 bi	-	-	134217728 bi	134217728 bi	134217728 bi	-	134217728 bi	134217728 bi
内存集成电路类型	SYNCHRONOUS DRAM	-	-	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	-	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
端口数量	1	-	-	1	1	1	-	1	1
字数	8388608 words	-	-	8388608 words	8388608 words	8388608 words	-	8388608 words	8388608 words
字数代码	8000000	-	-	8000000	8000000	8000000	-	8000000	8000000
工作模式	SYNCHRONOUS	-	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	-	-	85 °C	85 °C	85 °C	-	85 °C	85 °C
最低工作温度	-40 °C	-	-	-40 °C	-40 °C	-40 °C	-	-40 °C	-40 °C
输出特性	3-STATE	-	-	3-STATE	3-STATE	3-STATE	-	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	-	-	TSOP2	TSOP2	TSOP2	-	TSOP2	TSOP2
封装等效代码	TSOP54,.46,32	-	-	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	-	TSOP54,.46,32	TSOP54,.46,32
封装形状	RECTANGULAR	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	-	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
电源	3.3 V	-	-	3.3 V	3.3 V	3.3 V	-	3.3 V	3.3 V
认证状态	Not Qualified	-	-	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
刷新周期	4096	-	-	4096	4096	4096	-	4096	4096
座面最大高度	1.2 mm	-	-	1.2 mm	1.2 mm	1.2 mm	-	1.2 mm	1.2 mm
自我刷新	YES	-	-	YES	YES	YES	-	YES	YES
连续突发长度	1,2,4,8,FP	-	-	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	-	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.001 A	-	-	0.001 A	0.001 A	0.001 A	-	0.001 A	0.001 A
最大压摆率	0.21 mA	-	-	0.21 mA	0.21 mA	0.22 mA	-	0.21 mA	0.22 mA
最大供电电压 (Vsup)	3.6 V	-	-	3.6 V	3.6 V	3.6 V	-	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	-	-	3 V	3 V	3 V	-	3 V	3 V
标称供电电压 (Vsup)	3.3 V	-	-	3.3 V	3.3 V	3.3 V	-	3.3 V	3.3 V
技术	CMOS	-	-	CMOS	CMOS	CMOS	-	CMOS	CMOS
端子面层	Tin/Lead (Sn/Pb)	-	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子节距	0.8 mm	-	-	0.8 mm	0.8 mm	0.8 mm	-	0.8 mm	0.8 mm
处于峰值回流温度下的最长时间	NOT SPECIFIED	-	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED
宽度	10.16 mm	-	-	10.16 mm	10.16 mm	10.16 mm	-	10.16 mm	10.16 mm
Base Number Matches	1	-	-	1	1	1	-	1	1