K4S641633F-G(A)L/N/P
CMOS SDRAM
4Mx16
Mobile SDRAM
52CSP
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Revision 1.4
December 2002
Rev. 1.4 Dec. 2002
K4S641633F-G(A)L/N/P
1M x 16Bit x 4 Banks SDRAM in 52CSP
FEATURES
• 3.0V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70
°C).
Extended Temperature Operation (-25°C ~ 85°C).
Industrial Temperature Operation (-40°C ~ 85°C).
• 52balls CSP (-GXXX - Pb, -AXXX - Pb Free)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S641633F is 67,108,864 bits synchronous high data rate
Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fab-
ricated with SAMSUNG’s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock and I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance memory
system applications.
ORDERING INFORMATION
Part No.
K4S641633F-G(A)L/N/P75
K4S641633F-G(A)L/N/P1H
Max Freq.
133MHz(CL=3)
105MHz(CL=2)
105MHz(CL=2)
Interface Package
52CSP
LVCMOS
Pb
(Pb Free)
K4S641633F-G(A)L/N/P1L 105MHz(CL=3)
*1
-G(A)L ; Low Power, Operating Temp : -25°C ~ 70° C.
-G(A)N ; Low Power, Operating Temp : -25
°C
~ 85°C .
-G(A)P : Low Power, Operating Temp : -40°C ~ 85°C .
Note :
1. In case of 40MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
1M x 16
1M x 16
1M x 16
1M x 16
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 Dec. 2002
K4S641633F-G(A)L/N/P
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
6
A
B
C
D
E
D
F
D
1
G
H
J
D/2
K
L
M
N
E
E/2
5
4
3
2
1
e
CMOS SDRAM
< Top View
*2
>
52Ball(4x13) CSP
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Vss
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
CLK
CKE
A11
A8
A6
Vss
2
DQ15
V
SSQ
V
DDQ
DQ11
V
SSQ
V
DDQ
V
D D
UDQM
CS
A9
A7
A5
A4
5
DQ0
V
DDQ
V
SSQ
DQ4
V
DDQ
V
SSQ
Vss
LDQM
RAS
BA1
A0
A2
A3
6
V
D D
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
WE
CAS
BA0
A10
A1
V
D D
*2: Top View
Pin Name
CLK
A
A1
Max. 0.20
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
[Unit:mm]
CS
CKE
A
0
~ A
11
BA
0
~ BA
1
RAS
CAS
WE
L(U)DQM
D Q
0
~
15
V
DD
/V
SS
Encapsulant
b
z
*1: Bottom View
< Top View
*2
>
#A1 Ball Origin Indicator
K4S641633F
SEC
Week
V
DDQ
/V
SSQ
Symbol
A
A
1
E
E
1
D
D
1
e
b
z
Min
0.90
-
-
-
-
-
-
0.40
-
Typ
0.95
0.35
6.60
3.75
11.00
9.0
0.75
0.45
-
Max
1.00
-
-
-
-
-
-
0.5
0.10
XXXX
Rev. 1.4 Dec. 2002
K4S641633F-G(A)L/N/P
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
D D
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to V
SS
= 0V, T
A
=Commercial, Extended, Industrial Temperature)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
D D
V
DDQ
V
I H
V
IL
V
O H
V
OL
I
LI
Min
2.7
2.7
2.2
-0.3
2.4
-
-10
Typ
3.0
3.0
3.0
0
-
-
-
Max
3.6
3.6
V
DDQ
+0.3
0.5
-
0.4
10
Unit
V
V
V
V
V
V
uA
1
2
I
O H
= -2mA
I
OL
= 2mA
3
Note
Note
:
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
(V
D D
= 3.0V or 3.3V, T
A
= 23
°C,
f = 1MHz, V
R E F
=0.9V
±
50 mV)
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
D Q
0
~ DQ
15
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.0
2.0
2.0
3.5
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Note
Rev. 1.4 Dec. 2002
K4S641633F-G(A)L/N/P
DC CHARACTERISTICS
CMOS SDRAM
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
=Commercial, Extended, Industrial Temperature)
Parameter
Symbol
Test Condition
-75
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
I
CC1
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
I H
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
60
Version
-1H
55
-1L
55
mA
1
Unit
Note
I
C C 2
P
I
C C 2
PS
I
CC2
N
0.5
0.5
11
mA
Precharge Standby Current
in non power-down mode
CKE
≥
V
I H
(min), CLK
≤
V
IL
(max), t
C C
=
∞
I
CC2
NS
Input signals are stable
I
C C 3
P
I
C C 3
PS
I
CC3
N
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
I H
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
I H
(min), CLK
≤
V
IL
(max), t
C C
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
R C
(min)
-G(A)L
mA
8
5
5
22
mA
Active Standby Current
in power-down mode
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
22
mA
Operating Current
(Burst Mode)
Refresh Current
I
CC4
90
70
70
mA
1
I
CC5
135
120
120
mA
uA
2
3
4
5
Self Refresh Current
I
CC6
CKE
≤
0.2V
-G(A)N
-G(A)P
400
uA
uA
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S641633F-G(A)L**
4. K4S641633F-G(A)N**
5. K4S641633F-G(A)P**
6. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Rev. 1.4 Dec. 2002
