K8C12(13)15ET(B)M
FLASH MEMORY
512Mb M-die MLC NOR Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.2
October, 2006
K8C12(13)15ET(B)M
FLASH MEMORY
Document Title
512M Bit (32M x16) Sync Burst/Page Mode/Multi Bank MLC NOR Flash Memory
Revision History
Revision No. History
0.0
0.1
Initial
Draft Date
Remark
September 1, 2005 Advance
Advance
Revision
October 31, 2005
- Correct Icc2(Active Write Current) from 15mA(min), 30mA(max)
to 25mA(typ), 40mA(max)
- Correct default value of programmable wait state from A11~A14
"1010"(Data valid on the 14th active CLK) to "1011"(Data valid on the
15th active CLK)
- Correct the description of Figure 4(Continuous Burst Mode
Read@133MHz) for exact explanation of initial access time.
- Correct the description of Figure 5(Continuous Burst Mode
Read@108MHz) for exact explanation of initial access time.
- Correct the description of Figure 6(8 word Linear Burst Mode with
Wrap Around@133MHz) for exact explanation of initial access time.
- Correct the description of Figure 7(8 word Linear Burst with RDY Set
One Cycle Before Data) for exact explanation of initial access time.
- Correct tBA(Burst Access Time Valid Clock to Output Delay)
from 8ns(@83Mhz) to 9ns(@83MHz)
- Correct tBDH(Data Hold Time from Next Clock Cycle) from
4ns(@66MHz), 2.25ns(@108MHz), 1.5ns(@133MHz) to
3ns(@66MHz), 2ns(@108MHz), 2ns(@133MHz)
- Correct tRDYA(Clock to RDY Setup Time) from 8ns(@83Mhz) to
9ns(@83MHz)
- Correct tRDYS(RDY setup to Clock) from 4ns(@66MHz),
2.25ns(@108MHz), 1.5ns(@133MHz) to 3ns(@66MHz),
2ns(@108MHz), 2ns(@133MHz)
- Correct tOE(Output Enable to Output Valid) from 20ns to 15ns
- Correct typo
Revision
- Correct typo
- Delete tPRC(Page Read Cycle Time) from asynchornous read
paramter
- Modify figures for first word boundary crossing
- Modify output driver setting table
- Add Pin Configuration and Ball FBGA View
- Change tAVDH(AVD Hold Time from CLK) from 6ns @66MHz,
5ns @83MHz to 2ns @66/83MHz
- Add Ordering Information for Density
12 : 512Mb for 66/83MHz, 13 : 512Mb for 108/133Mhz
- Add Product Classification Table (Table 1-1)
- CFI note is added (Max Operation frequency : Data 53H is in 66/
83Mhz part
- Specification is finalized
- Correct typo
0.2
December 20, 2005 Advance
0.3
April 04, 2006
Advance
1.0
June 08, 2006
1.1
- Active Asynchronous read Current(@1Mhz) is changed
September 08,2006
3mA(typ.),5mA(max.) to 8mA(typ.), 10mA(max.)
'In erase/program suspend followed by resume operation, min. 200ns
is needed for checking the busy status' is added
- Frequency information is added to Programmable Wait State at Burst
Mode Configuration Register Table.
- "Asynchronous mode may not support read following four sequential
invalid read condition within 200ns." is added
2
Revision 1.2
October, 2006
K8C12(13)15ET(B)M
Revision No. History
1.2
FLASH MEMORY
Draft Date
Remark
Correct typo.
October 17, 2006
In Write Buffer Programming, "And from third cycle to the last cycle of
Write to Buffer command is also required when using Write-Buffer-Pro-
gramming feature in Unlock Bypass mode." is added
3
Revision 1.2
October, 2006
K8C12(13)15ET(B)M
FLASH MEMORY
512M Bit (32M x16) Sync Burst/Page Mode/Multi Bank MLC NOR Flash Memory
FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 33,554,432 x 16 bit ( Word Mode Only)
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (32Mb Partition)
•
OTP Block : Extra 512-Word block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time : 110ns
- Synchronous Random Access Time :110ns
- Burst Access Time :
11ns (66MHz) / 9ns (83MHz) / 7ns (108MHz) / 6ns (133MHz)
•
Page Mode Operation
16Words Page access allows fast asychronous read
Page Read Access Time : 15ns
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
•
Block Architecture
- Four 16Kword blocks and five hundred eleven 64Kword blocks
- Bank 0 contains four 16 Kword blocks and thirty-one 64Kword
blocks
- Bank 1 ~ Bank 15 contain four hundred eighty 64Kword blocks
•
Reduce program time using the V
PP
•
Support 32 words Buffer Program
•
Power Consumption (Typical value, C
L
=30pF)
- Synchronous Read Current : 35mA at 133MHz
- Program/Erase Current : 25mA
- Read While Program/Erase Current : 45mA
- Standby Mode/Auto Sleep Mode : 30uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Deep Power Down Mode
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
100K Program/Erase Cycles Minimum
•
Data Retention : 10 years
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Output Driver Control by Configuration Register
•
Package : 167-Ball FBGA type, 10.5mm x 14.0mm
0.8 mm ball pitch
1.4 mm (Max.) Thickness
GENERAL DESCRIPTION
The K8C12(13)15E featuring single 1.8V power supply is a
512Mbit Burst Multi Bank Flash Memory organized as 32Mx16.
The memory architecture of the device is designed to divide its
memory arrays into 515 blocks with independent hardware pro-
tection. This block architecture provides highly flexible erase
and program capability. The K8C12(13)15E NOR Flash con-
sists of sixteen banks. This device is capable of reading data
from one bank while programming or erasing in the other bank.
Regarding read access time, the K8C1215E provides 11ns
burst access time and 110ns initial access time at 66MHz. At
the K8C1215E provides 9ns burst access time and 110ns initial
access time at 83MHz.At the K8C1315E provides 7ns burst
access time and 110ns initial access time at 108MHz. At
133MHz, the K8C1315E provides 6ns burst access time and
110ns initial access time.
The device performs a program operation in units of 16 bits
(Word) and erases in units of a block. Single or multiple blocks
can be erased. The block erase operation is completed within
typically 0.6sec. The device requires 15mA as program/erase
current in the extended temperature ranges.
The K8C12(13)15E NOR Flash Memory is created by using
Samsung's advanced CMOS process technology.
PIN DESCRIPTION
Pin Name
A0 - A24
DQ0 - DQ15
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
DPD
Vcc
V
SS
Pin Function
Address Inputs
Data input/output
Chip Enable
Output Enable
Hardware Reset Pin
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Deep Power Down
Power Supply
Ground
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
4
Revision 1.2
October, 2006
K8C12(13)15ET(B)M
Pin Configuration
1
2
3
4
5
6
7
8
9
10
FLASH MEMORY
11
12
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
DNU
DNU
DNU
DNU
DNU
V
SS
NC
A17
V
CC
NC
NC
WE
NC
V
SS
NC
NC
WP
A1
A4
A7
VPP
NC
NC
V
SS
A9
A15
A22
NC
NC
A2
A5
A18
RDY
A21
RESET
A20
A10
A11
A14
A23
NC
A3
A6
NC
NC
CLK
NC
A19
A12
A13
NC
V
SS
NC
V
SS
NC
NC
NC
AVD
NC
A8
NC
NC
NC
NC
NC
NC
NC
NC
NC
A24
A16
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DPD
DQ13
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ8
DQ9
NC
NC
NC
V
SS
NC
V
SS
NC
NC
NC
A0
DQ4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ1
DQ11
DQ12
DQ6
NC
NC
NC
NC
V
SS
NC
CE
DQ0
DQ2
DQ10
DQ5
DQ14
DQ7
DQ15
NC
V
CC
V
SS
NC
OE
V
CCQ
V
CCQ
DQ3
NC
V
CCQ
V
CCQ
NC
V
CC
NC
NC
NC
V
SS
NC
NC
NC
V
SS
NC
V
SS
NC
NC
DNU
DNU
DNU
DNU
DNU
DNU
167-FBGA : Top View (Ball Down)
5
Revision 1.2
October, 2006
嵌入式系统
