KM68V4000BZ, KM68U4000BZ Family
Document Title
512Kx8 Low Voltage & Low Power SRAM
Data Sheets for 48-CSP
Preliminary
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
History
- 1′st edition
- Package Dimension Finalized
Draft Data
Feb. 4′th, 1997
Remark
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics reserve CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of
this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters
.
Revision 0.0
February 1997
KM68V4000BZ, KM68U4000BZ Family
512Kx8 bit Low Power and Low Voltage CMOS SRAM
with 48-CSP(Chip Scale Package)
FEATURES
¡Ü
¡Ü
Preliminary
CMOS SRAM
GENERAL DESCRIPTION
The KM68V4000BZ and KM68U4000BZ family are fabricated
by SAMSUNG′s advanced Full CMOS process technology. The
family can support various operating temperature ranges and
has very small size with 0.75 ball pitch and 6 x 8 ball array. The
family also support low data retention voltage for battery back-
up operation with low data retention current.
¡Ü
¡Ü
¡Ü
¡Ü
Process Technology : 0.4µm CMOS
Organization : 512Kx8
Power Supply Voltage
KM68V4000BZ Family : 3.3V±0.3V
KM68U4000BZ Family : 3.0V±0.3V
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 48-CSP with 0.75mm ball pitch
PRODUCT FAMILY
Power Dissipation
Product
Family
KM68V4000BLZ-L
KM68U4000BLZ-L
KM68V4000BLZI-L
KM68U4000BLZI-L
Operating
Temp.Range
Commercial
(0~70°C)
Industrial
(-40~85°C)
Vcc Range
Speed
(ns)
85
100
85
100
Standby
(I
SB1
)
15µA
(Max)
20µA
(Max)
Operating
(I
CC2
)
70mA(Max)
70mA(Max)
70mA(Max)
70mA(Max)
48-CSP
(6x8 ball area with
0.75mm ball pitch)
PKG Type
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
48-CSP PIN TOP VIEW
1
A
B
C
D
E
F
G
H
A
0
I/O
5
I/O
6
V
SS
V
CC
I/O
7
I/O
8
A
9
OE
A
10
A
18
CS
A
11
A
17
A
16
A
12
A
15
A
13
2
A
1
A
2
3
N.C
WE
NC
4
A
3
A
4
A
5
5
A
6
A
7
6
A
8
I/O
1
I/O
2
V
CC
V
SS
I/O
3
I/O
4
A
14
FUNCTIONAL BLOCK DIAGRAM
X-Decorder
A
2~7
, A
12
,
A
14
, A
16
, A
18
Cell
Array
A
0
, A
1
, A
8~11
,
A
13
, A
15
, A
17
Y-Decorder
Control
Logic
I/O Buffer
I/O
1~8
CS, WE, OE
Name
A
0
~A
18
WE
CS
OE
Function
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Name
Vcc
Vss
Function
Power
Ground
I/O
1
~I/O
8
Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD.
reserves the right
to change products and specifications without notice.
Revision 0.0
February 1997
KM68V4000BZ, KM68U4000BZ Family
PRODUCT LIST & ORDERING INFORMATION
PRODUCT LIST
Commercial Temp Product
(0~70°C)
Part Name
KM68V4000BLZ-8L
KM68U4000BLZ-10L
Function
48-CSP, 85ns, 3.3V, LL
48-CSP, 100ns, 3.0V, LL
Part Name
KM68V4000BLZI-8L
KM68U4000BLZI-10L
Preliminary
CMOS SRAM
Industrial Temp Product
(-40~85°C)
Function
48-CSP, 85ns, 3.3V, LL
48-CSP, 100ns, 3.0V, LL
ORDERING INFORMATION
KM6 8 X 4000 B X X X - X X
L-Low Low Power, Blank-Low Power or Normal Power
Access Time : 8=85ns, 10=100ns
Operating Temperature : Blank=Commercial, I=Industrial
Package Type : T=TSOP Forward, R=TSOP Reverse
Z=48-CSP with 0.75mm pitch
L-Low Power, LL-Low Low Power, Blank-Normal Power
Die Version : B=2′nd revision
Density : 4000=4Mbit
V=3.0~3.6V, U=2.7~3.3V
Organization : 8= x8
SEC Standard SRAM
Revision 0.0
February 1997
KM68V4000BZ, KM68U4000BZ Family
ABSOLUTE MAXIMUM RATINGS
*
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
0.7
-65 to 150
0 to 70
Operating Temperature
T
A
-40 to 85
Soldering temperature and time
T
SOLDER
260°C, 10sec(Lead Only)
°C
-
Unit
V
V
W
°C
°C
Preliminary
CMOS SRAM
Remark
-
-
-
-
KM68V4000BLZ-L
KM68U4000BLZ-L
KM68V4000BLZI-L
KM68U4000BLZI-L
-
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional opera tion should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect r eliability.
RECOMMENDED DC OPERATING CONDITIONS
*
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
KM68V4000BZ Family
KM68U4000BZ Family
All Family
KM68V4000BZ Family
KM68U4000BZ Family
KM68V4000BZ Family
KM68U4000BZ Family
Min
3.0
2.7
0
2.2
2.2
-0.3***
-0.3***
Typ**
3.3
3.0
0
-
-
-
-
Max
3.6
3.3
0
Vcc+0.3
Vcc+0.3
0.4
0.4
Unit
V
V
V
V
V
V
V
* 1) Commercial Product : T
A
=0 to 70°C, unless otherwise specified
2) Industrial Product : T
A
=-40 to 85°C, unless otherwise specified
** T
A
=25°C
*** V
IL
(Min)=-3.0V for
≤30ns
pulse width
CAPACITANCE*
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
* Capacitance is sampled not, 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
Revision 0.0
February 1997
KM68V4000BZ, KM68U4000BZ Family
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
V
IN
=Vss to Vcc
CS=V
IH
or V
IL,
V
IO
=Vss to Vcc
CS=V
IL
, V
IN
=V
IH
or V
IL
,
I
I0
=0mA
Cycle time=1µs100%duty
CS≤0.2V, V
IL
≤0.2V,
V
IH
≥Vcc-0.2V,
I
IO
=0mA
Read
Write
Read
Write
Test Conditions*
Min
-1
-1
-
-
-
-
-
-
2.4
-
Low Low Power
Low Low Power
I
SB1
KM68U4000BLZ-L
KM68U4000BLIZ-L
CS≥Vcc-0.2V, Others=0~Vcc
Low Low Power
Low Low Power
-
-
-
-
Preliminary
CMOS SRAM
Typ**
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
1
1
20
40
20
Unit
µA
µA
mA
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
KM68V4000BLZ-L
Standby
Current
(CMOS)
KM68V4000BLZI-L
V
OL
V
OH
I
SB
mA
40
90
0.4
-
0.5
15
20
15
20
mA
V
V
mA
µA
µA
µA
µA
Min cycle, 100%duty, I
IO
=0mA, CS=V
IL
,V
IN
=V
IH
or V
IL
I
OL
=2.1mA
I
OH
=-1.0mA
CS=V
IH
* 1) Commercial Product : T
A
=0 to 70°C, Vcc=3.3±0.3V (68V4000BLZ/-L Family), Vcc=3.0±0.3V (68U4000BLZ/-L Family)
2) Industrial Product : T
A
=-40 to 85°C, Vcc=3.3±0.3V (68V4000BLZI/-L Family), Vcc=3.0±0.3V (68U4000BLZI/-L Family)
** T
A
=25°C
A.C OPERATING CONDITIONS
TEST CONDITIONS
(1.Test Load and Test Input/Output Reference)*
Item
Input pulse level
Input rising and falling time
input and output reference voltage
Output load (See right)
* See DC Operating conditions
Value
0.4 to 2.2V
5ns
1.5V
C
L
=100pF+1TTL
Remark
-
-
-
-
* Including scope and jig capacitance
C
L
*
Revision 0.0
February 1997
