Surface Mount and Through-Hole Multilayer Ceramic Chip Stacked Capacitors
KPS MIL Series, SMPS Stacked Capacitors,
MIL–PRF–49470, DSCC 87106, 25 – 1,000 VDC
(Commercial, Military and Space Grades)
Overview
KEMET Power Solutions (KPS) MIL Series ceramic
stacked capacitors are available in commercial, military
and space grades and are well suited for standard and
high reliability switch mode power supply (SMPS) and
pulse energy applications. Qualified under performance
specification MIL–PRF–49470, our military and space
grade products meet or exceed the requirements outlined
by DSCC (Defense Supply Center, Columbus) and are
available in both B (standard reliability) & T (high reliability)
product levels. MIL–PRF–49470 was developed as part
of a cooperative effort between the U.S. Military, NASA
and SMPS suppliers to produce a robust replacement to
cancelled DSCC Drawing 87106.
The KPS MIL Series is constructed using large chip
multilayer ceramic capacitors (MLCCs), horizontally
stacked and secured to a lead-frame termination system
using a high melting point (HMP) solder alloy. The lead frame
isolates the MLCCs from the printed circuit board (PCB) while
establishing a parallel circuit configuration. Mechanically
isolating the capacitors from the PCB improves mechanical
and thermal stress performance, while the parallel circuit
configuration allows for bulk capacitance in the same or
smaller design footprint.
Available in BX, BR, BQ, and X7R dielectrics, these devices are
available in unencapsulated styles in both surface mountable
and through-hole configurations. Their low Equivalent Series
Resistance (ESR) and Equivalent Series Inductance (ESL)
make them ideally suited for input and output filtering
of power supply as well as snubber applications. The
encapsulated styles are primarily used where increased
mechanical and environmental protection is required, such as
in avionics systems.
Benefits
• −55°C to +125°C operating temperature range
• High frequency performance
• Bulk capacitance in a reduced footprint
• MIL–PRF–49470 QPL
• Military Case Codes 3, 4 and 5
• Space Grade available (“T” Level)
• DSCC approved (87106)
• Commercial/Industrial Grade available
• Customer specific requirements available
• Low ESR and ESL
• High thermal stability
• High ripple current capability
• Higher reliability than aluminum electrolytic or tantalum
Applications
• Military
• Space
• Industrial
• Input and output filtering on power supplies – often found
on “capacitor banks“
• Snubber circuits
• Radar filtering (28 V/microwave burst)
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© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
C1031_KPS_SMPS_49470_STACKS • 4/17/2020
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Surface Mount and Through-Hole Multilayer Ceramic Chip Stacked Capacitors – KPS MIL Series, SMPS Stacked Capacitors
MIL–PRF–49470 Ordering Information
M49470
Performance Specification
Indicating MIL-PRF-49470
1
M49470 = B level
T49470 = T level
A T prefix is used in place of
the M for T level product.
1
R
01
474
K
C
Rated
Voltage
(VDC)
A = 50
B = 100
C = 200
E = 500
N
Lead
Configuration
4
N = Straight Pin
L = Formed L
J = Formed J
Dielectric
Performance Specification Sheet Number
Capacitance Capacitance
Classification/
Code (pF)
Tolerance
(Indicating MIL-PRF-49470/1)
3
Characteristic
2
Q = BQ
R = BR
X = BX
01 = Unencapsulated
Two
significant
digits and
number of
zeros
J = ±5%
K = ±10%
M = ±20%
Indicates performance and reliability requirements. "B" level represents standard reliability."T" level represents high reliability.
1
Please refer to performance specification sheet MIL–PRF–49470 for details regarding test levels. The latest revision of the specification sheet is
available through DSCC.
1, 3
Test level option "T" is not available on encapsulated stacked devices (i.e. MIL–PRF–49470/2).
2
Dielectric classification and characteristic details are outlined in the "Electrical Parameters" section of this document.
4
Lead configuration and dimension details are outlined in the "Dimensions" section of this document.
KPS MIL Series, SMPS Stacks Ordering Information
(Do not use this ordering code if a QPL MIL–SPEC part type is required. Please order using MIL–SPEC ordering code.
Details regarding MIL–PRF–49470 QPL ordering information is outlined above.)
L1
Product Family
1
L1 = Unencapsulated
R
N
30
C
106
K
S
Testing Option
4
B = M49470 B level
T = M49470 T level
C = DSCC87106
S = Commercial
X = Non-standard
(Customer specific
requirements)
12
Maximum Height
Dimension (in.)
5
Unencapsulated
12 = 0.12"
24 = 0.24"
36 = 0.36"
48 = 0.48"
65 = 0.65"
Encapsulated
27 = 0.27"
39 = 0.39"
53 = 0.53"
66 = 0.66"
80 = 0.80"
Dielectric
Case Size/
Rated
Lead
Capacitance Capacitance
Classification/
Case Code
Voltage
Configuration
3
Code (pF)
Tolerance
Characteristic
2
(CC)
(VDC)
Q = BQ
R = BR
X = BX
W = X7R
N = Straight
L = Formed L
J = Formed J
30 = CC 3
40 = CC 4
50 = CC 5
3 = 25
Two
5 = 50
significant
1 = 100
digits and
2 = 200
number of
C = 500
zeros
B = 630
D = 1,000
J = ±5%
K = ±10%
M = ±20%
Test level option "T" is not available on encapsulated stacked devices, i.e., MIL–PRF–49470/2. If a QPL MIL–Spec part type is required, please order
using the MIL–Spec ordering code.
2
Dielectric classification and characteristic details are outlined in the "Electrical Parameters" section of this document.
3
Lead configuration and dimension details are outlined in the "Dimensions" section of this document. Additional lead configurations may be available.
Contact KEMET for details.
4
Indicates performance and reliability requirements. Testing option details are outlined in the "Performance & Reliability" section of this document.
4
Please refer to performance specification sheet MIL–PRF–49470 for additional details regarding test levels. The latest revision of the specification
sheet is available through DSCC.
4
DSCC Drawing 87106 was cancelled on 01/03/2005. MIL–PRF–49470 capacitors are preferred over DSCC Drawing 87106 capacitors.
5
Maximum height dimensions are provided in product tables 1A, 1B, and 1C of this document
1, 4
Ordering Information Requirements per DSCC Drawing 87106
DSCC Drawing 87106 was cancelled on 01/03/2005. Customers can continue to order per 87106 requirements using the original DSCC ordering code,i.e.,
87106–001.
When available, MIL–PRF–49470 devices are preferred over DSCC Drawing 87106. The MIL–PRF–49470 military specification product provides
additional quality assurance provisions that are not required by the DSCC drawing. These extra provisions create a more robust replacement.
© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
C1031_KPS_SMPS_49470_STACKS • 4/17/2020
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Surface Mount and Through-Hole Multilayer Ceramic Chip Stacked Capacitors – KPS MIL Series, SMPS Stacked Capacitors
(M49470/1 & L1) Product Dimensions – Inches (Millimeters)
Case
Code
3
4
5
1
C
Lead Spacing
±0.025 (0.635)
0.450 (11.43)
0.400 (10.16)
0.250 (6.35)
E
Length
Maximum
0.500 (12.70)
0.440 (11.18)
0.300 (7.62)
D
D
Width
Width
Minimum Maximum
0.950 (24.13) 1.075 (27.30)
A
Height
Maximum
Seating Plane
1
±0.010 (0.250)
Number
of Leads
per Side
10
4
3
Mounting
Technique
Solder reflow
only
Refer to tables
1A and 1C
0.350 (8.89) 0.425 (10.80)
for specific
maximum A
0.224 (5.69) 0.275 (6.98)
dimension
0.055 (1.40)
Only applies to lead style "N" (straight).
Circuit Diagram
D
Lead Style N
E
Lead Style J
E
Lead Style L
E
A
B
See
See
Note 5 Note 5
Seating Plane
See Note 4
See Note 7
See 0.100 Maximum
Note 6 0.025 Minimum
0.100
Typical
0.020
±0.002
0.010 RAD
Typical
0.055 Maximum
C
0.250 Minimum
0.250
Minimum
0.055
Maximum
C
L
0.010 RAD
Typical
0.055 Maximum
L
0.050
Minimum
0.010
±0.002
C
0.050
Minimum
1. Dimensions are in inches.
2. Metric equivalents are given for general information only.
3. Unless otherwise specified, tolerances are ±0.010 inch (0.25 mm).
4. Lead frame configuration is shown as typical above the seating plane. The seating plane shall be configured to create a standoff height of 0.055 inch
±0.010 inch when the part is mounted to a printed circuit board (PCB). The standoff height shall be the distance between the PCB and the bottom of
the chip stack. A seating plane is only required for lead style N.
5. See Table 1 for specific maximum A dimension. For maximum B dimension, add .065 inch (1.65 mm) to the appropriate A dimension. For all lead
styles, the number of chips is determined by the capacitance and voltage rating.
6. For case code 5, dimensions shall be .100 inch (2.54 mm) maximum and 0.012 inch (0.30 mm) minimum.
7. Lead alignment within pin rows shall be within ±0.005 inch (0.13 mm). Lead alignment between pin rows shall be within one half of the lead width
(0.010 inch (0.25 mm)).
Lead Configurations – Inches (Millimeters)
Lead Style
Symbol
N
L
J
Lead Style
(N) Straight
(L) Formed
(J) Formed
L
Lead Length
0.250 Minimum (6.35)
0.070 ±0.010 (1.78 ±0.25)
0.070 ±0.010 (1.78 ±0.25)
Additional lead configurations may be available. Contact KEMET for details.
© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
C1031_KPS_SMPS_49470_STACKS • 4/17/2020
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Surface Mount and Through-Hole Multilayer Ceramic Chip Stacked Capacitors – KPS MIL Series, SMPS Stacked Capacitors
Qualification Inspection Per MIL–PRF–49470
Inspection
Group I
Thermal shock and voltage
conditioning
Visual and mechanical
Inspection
Low temperature storage
Barometric pressure
Terminal strength
Voltage-temperature limits
Vibration, high frequency
Immersion
Shock, specified pulse
Resistance to soldering heat
Moisture resistance
DPA (T level only)
4.8.5
Test Method Paragraph
Group II
4.8.4
Group III
4.8.23
4.8.9
4.8.10
4.8.13.1
4.8.14
4.8.15
4.8.16
4.8.17
4.8.18
4.8.19
Group IV
Group V
Group VI
Group VII
Humidity, steady state, low voltage
4.8.21
(T level only)
Group VIII
Life
4.8.22
Environmental Compliance
These devices do not meet RoHS criteria
© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
C1031_KPS_SMPS_49470_STACKS • 4/17/2020
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Surface Mount and Through-Hole Multilayer Ceramic Chip Stacked Capacitors – KPS MIL Series, SMPS Stacked Capacitors
Electrical Parameters/Performance Characteristics: BQ Dielectric
Item
Operating Temperature Range
Capacitance Change with Reference to
+25°C and 0 VDC Applied (TCC)
Capacitance Change with Reference to
+25°C and 100% Rated VDC Applied
Aging Rate (Maximum % Capacitance Loss/Decade Hour)
Dielectric Withstanding Voltage (DWV)
Dissipation Factor (DF) Maximum Limit at 25ºC
Insulation Resistance (IR) Limit at 25°C
Insulation Resistance (IR) Limit at 125°C
−55°C to +125°C
±15%
+15%, −50%
1%
250% of rated DC voltage for voltage rating < 500 V
150% of rated DC voltage for voltage rating of 500 V
(5±1 seconds and charge/discharge not exceeding 50 mA)
2.5%
1,000 megohm microfarads (minimum) or 100 GΩ
100 megohm microfarads (minimum) or 10 GΩ
Parameters/Characteristics
Regarding aging rate: Capacitance measurements (including tolerance) are indexed to a referee time of 1,000 hours.
To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.
Capacitance and dissipation factor (DF) measured under the following conditions:
1 kHz ±100 Hz at 1.0 Vrms ±0.2 Vrms
Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known
as Automatic Level Control (ALC). The ALC feature should be switched to "ON."
Electrical Parameters/Performance Characteristics: BR Dielectric
Item
Operating Temperature Range
Capacitance Change with Reference to
+25°C and 0 VDC Applied (TCC)
Capacitance Change with Reference to
+25°C and 100% Rated VDC Applied
Aging Rate (Maximum % Capacitance Loss/Decade Hour)
Dielectric Withstanding Voltage (DWV)
Dissipation Factor (DF) Maximum Limit at 25ºC
Insulation Resistance (IR) Limit at 25°C
Insulation Resistance (IR) Limit at 125°C
−55°C to +125°C
±15%
+15%, −40%
1%
250% of rated DC voltage for voltage rating < 500 V
150% of rated DC voltage for voltage rating of 500 V
(5±1 seconds and charge/discharge not exceeding 50 mA)
2.5%
1,000 megohm microfarads (minimum) or 100 GΩ
100 megohm microfarads (minimum) or 10 GΩ
Parameters/Characteristics
Regarding aging rate: Capacitance measurements (including tolerance) are indexed to a referee time of 1,000 hours.
To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.
Capacitance and dissipation factor (DF) measured under the following conditions:
1 kHz ±100 Hz at 1.0 Vrms ±0.2 Vrms
Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known
as Automatic Level Control (ALC). The ALC feature should be switched to "ON."
© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
C1031_KPS_SMPS_49470_STACKS • 4/17/2020
5
微控制器 MCU
