Noise filters connected to SCL1, SDA1, SCL2 and SDA2 pins
Incorporates a feature to prohibit write operations under low voltage conditions.
* : I
2
C Bus is a trademark of Philips Corporation.
** : DDC and EDID are trademarks of Video Electronics Standard Association (VESA).
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
July, 2013
62012 SY 20120111-S00002 No.A2069-1/21
LE24CBK23MC
Package Dimensions
unit:mm (typ)
3434
4.9
8
3.9
6.0
1
2
0.4
1.75 MAX
0.2
(0.55)
1.27
SANYO : SOP8J(200mil)
Pin Assignment
0.15
(1.5)
0.64
Pin Descriptions
PIN.1
SCL2
SDA2
COBM#
GND
SDA1
SCL1
WP#
VDD
Clock input
Data input/output
Bank/Combine mode change
Ground
Data input/output
Clock input
Write protection
Power supply
Bank1
Bank2
SCL2
SDA2
COBM#
GND
1
2
3
4
(Top view)
8
7
6
5
VDD
WP#
SCL1
SDA1
PIN.2
PIN.3
PIN.4
PIN.5
PIN.6
PIN.7
PIN.8
No.A2069-2/21
LE24CBK23MC
Block Diagram
Bank1
Write controller
Input Buffer
Condition detector
High voltage generator
Address generator
SCL1
Serial controller
X decoder
EEPROM Array
(2K-bit)
Input Buffer
SCL2
Bank Controller & Mode Decoder
Y decoder & Sense AMP
Serial-Parallel converter
SDA1
I/O Buffer
Bank2
Write controller
Condition detector
High voltage generator
I/O Buffer
Address generator
SDA2
Serial controller
X decoder
EEPROM Array
(2K-bit)
COBM#
WP#
Input Buffer
Y decoder & Sense AMP
Serial-Parallel converter
Description of Operation
The Bank1 control signals are SCL1 and SDA1, and the Bank2 control signals are SCL2 and SDA2. The control
signals for each bank can be controlled separately, regardless of the other bank’s status. This enables the product to
be handled like two separate EEPROM mounted in a single package, which means that the Bank1 and Bank2 sides
can be used simultaneously for two independent systems.
Bank mode (2K bits + 2K bits) and combine mode (internally handled as 4K bits) can be switched using the COBM#
pin. In combine mode, the Bank1 control signals (SCL1, SDA2) are used, and both Bank1 and Bank2 are accessed.
This enables the two-bank configuration (2K bits + 2K bits) to be used as a pseudo-one-bank configuration (4K bits),
which allows access to both the Bank1 and Bank2 areas using a single system of control signals (SCL1, SDA1). Data
correlation is guaranteed between combine mode and bank mode, enabling operation while switching the mode, such
as performing write in combine mode and read in bank mode.
No.A2069-3/21
LE24CBK23MC
Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
DC input voltage
Over-shoot voltage
Storage temperature
Tstg
Below 20ns
Symbol
Conditions
Ratings
-0.5 to +6.5
-0.5 to +5.5
-1.0 to +6.5
-65 to +150
Unit
V
V
V
°C
Note: If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Operating Conditions
Parameter
Operating supply voltage
Operating temperature
Symbol
Conditions
Ratings
2.5 to 5.5
-40 to +85
Unit
V
°C
DC Electrical Characteristics
Parameter
Supply current at reading
(when either Bank1 or Bank2 is read)
Supply current at reading
(when both Bank1 and Bank2 are read
simultaneously)
Supply current at writing
(when either Bank1 or Bank2 is write)
Supply current at writing
(when both Bank1 and Bank2 are write
simultaneously)
Standby current
Input leakage current
Output leakage current (SDA)
Input low voltage
Input high voltage
Input low voltage(WP# pin)
Input high voltage(WP# pin)
ISB
ILI
ILO
VIL
VIH
VIL_WP
VIH_WP
VOL
Output low level voltage
VDD < 4.0V
*1)
IOL=0.7mA, VDD=2.5V
IOL=3.0mA, VDD=2.5V
IOL=3.0mA, VDD=5.5V
IOL=6.0mA, VDD=4.5V
*1: The actual VIH value of the WP# pin is 2.0V (VDD = 5.0V).
VDD*0.7
0.2
0.4
0.4
0.6
VDD*0.7
VDD*0.2
VIN=VDD or GND
VIN=GND to VDD
VOUT=GND to VDD
-2.0
-2.0
0.7
5
+2.0
+2.0
VDD*0.3
μA
μA
μA
V
V
V
V
V
V
V
V
ICC22
f=400kHz, tWC=5ms
8
mA
ICC21
f=400kHz, tWC=5ms
5
mA
ICC12
f=400kHz
1.6
mA
Symbol
ICC11
f=400kHz
Conditions
min
VDD=2.5V to 5.5V
typ
max
0.8
mA
Unit
Capacitance/Ta=25°C,
f=100kHz
Parameter
In/Output capacitance
Input capacitance
Symbol
CI/O
CI
Conditions
VI/O=0V (SDA)
VIN=0V (Other SDA)
min
typ
2
2
max
5
5
Unit
pF
pF
Note: This parameter is sampled and not 100% tested.
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