If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
–V
SS
)
Voltage at Any Pin
Power Dissipation (Note 3)
ESD Susceptability (Note 4)
Junction Temperature
15V
V
SS
− 0.2V to V
DD
+ 0.2V
150 mW
1800V
150˚C
Operating Ratings
(Notes 1, 2)
T
MIN
Temperature Range
T
MIN
≤T
A
≤T
MAX
Supply Voltage (V
DD
− V
SS
)
0˚C
≤T
A
≤
+70˚C
4.5V to 12V
T
A
T
MAX
Electrical Characteristics
(Notes 1, 2)
The following specifications apply for all channels with V
DD
= +6V, V
SS
= −6V, V
IN
= 5.5 Vpk, and f = 1 kHz, unless otherwise
specified. Limits apply for T
A
= 25˚C. Digital inputs are TTL and CMOS compatible.
Symbol
Parameter
Conditions
LM1973
Typical
(Note 5)
I
S
THD+N
XTalk
SNR
Supply Current
Total Harmonic Distortion
plus Noise
Crosstalk (Channel Separation)
(Note 7)
Signal-to-Noise Ratio
Inputs are AC Grounded
V
IN
= 0.5 Vpk
@
0dB Attenuation
0dB Attenuation for V
IN
V
CH
measured
@
−76dB
Inputs are AC Grounded
@
−12dB Attenuation
Limit
(Note 6)
5
0.003
Units
(Limits)
mA (max)
% (max)
dB
3
0.0008
110
120
104
110
96
dB (min)
dB (min)
dB (max)
dB (max)
dB (max)
dB (min)
dB (min)
dB (min)
dB (min)
dB (min)
dB (max)
dB (max)
nA (max)
kΩ (min)
kΩ (max)
nA (max)
MHz (max)
V (min)
V (max)
V (max)
V (min)
A-Weighted
A
M
Mute Attenuation
Attenuation Step Size Error
0dB to −16dB
−17dB to −48dB
−49dB to −76dB
Absolute Attenuation Error
Attenuation
@
0dB
Attenuation
@
−20dB
Attenuation
@
−40dB
Attenuation
@
−60dB
Attenuation
@
−76dB
Channel-to-Channel Attenuation
Tracking Error
I
LEAK
R
IN
I
IN
f
CLK
V
IH
V
IL
Analog Input Leakage Current
AC Input Impedance
Input Current
Clock Frequency
High-Level Input Voltage
Low-Level Input Voltage
Data-Out Levels (Pin 12)
@
Pins 9, 10, 11
@
Pins 9, 10, 11
±
0.05
±
0.1
±
0.25
0.01
19.8
39.5
59.3
74.5
0.5
19.0
38.5
58.0
73.0
Attenuation
@
0dB, −20dB, −40dB, −60dB
Attenuation
@
−76dB
Inputs are AC Grounded
Pins 2, 4, 18, V
IN
= 1.0 Vpk, f = 1 kHz
@
Pins 9, 10, 11
@
0V
±
0.5
±
0.75
10.0
40
1.0
3
100
20
60
<
V
IN
<
5V
±
100
2
2.0
0.8
0.1
5.9
V
DD
=6V, V
SS
=0V
Note 1:
Absolute Maximum Ratings
indicate limits beyond which damage to the device may occur.
Operating Ratings
indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Electrical Characteristics
state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given, however, the typical value is a good indication of device performance.
Note 2:
All voltages are measured with respect to GND (pins 1, 3, 5, 14, 17), unless otherwise specified.
Note 3:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
θ
JA
, and the ambient temperature T
A
. The maximum
allowable power dissipation is PD = (T
JMAX
− T
A
)/θ
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For the LM1973N, T
JMAX
= +150˚C,
and the typical junction-to-ambient thermal resistance, when board mounted, is 65˚C/W.
Note 4:
Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5:
Typicals are measured at 25˚C and represent the parametric norm.
www.national.com
2
LM1973
Electrical Characteristics
(Notes 1, 2)
Timing Diagram
(Continued)
Note 6:
Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 7:
At the present time the Crosstalk measurement is specified as a typical only, which is due to a hardware limitation of the automated test equipment.
01195803
FIGURE 2. Timing Diagram
Pin Descriptions
Signal Ground (1, 5, 17):
Each input has its own indepen-
dent ground, GND1, GND2, and GND3.
Signal Input (2, 4, 18):
There are 3 independent signal
inputs, IN1, IN2, and IN3.
Signal Output (6, 16, 20):
There are 3 independent signal
outputs, OUT1, OUT2, and OUT3.
Voltage Supply (13, 15):
Positive voltage supply pins, V
DD1
and V
DD2
.
Voltage Supply (7, 19):
Negative voltage supply pins, V
SS1
and V
SS2
. To be tied to ground in a single supply configura-
tion.
AC Ground (3, 14):
These two pins are not physically con-
nected to the die in any way (i.e., No bondwires). These pins
must be AC grounded to prevent signal coupling between
any of the pins nearby. Pin 14 should be connected to pins
13 and 15 for ease of wiring and the best isolation.
Logic Ground (8):
Digital signal ground for the interface
lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.
Clock (9):
The clock input accepts a TTL or CMOS level
signal. The clock input is used to load data into the internal
shift register on the rising edge of the input clock waveform.
Load/Shift (10):
The load/shift input accepts a TTL or
CMOS level signal. This is the enable pin of the device,
allowing data to be clocked in while this input is low (0V).
Data-In (11):
The data-in input accepts a TTL or CMOS level
signal. This pin is used to accept serial data from a micro-
controller that will be latched and decoded to change a
channel’s attenuation level.
Data-Out (12):
This pin is used in daisy-chain mode where
more than one µPot is controlled via the same data line. As
the data is clocked into the chain from the µC, the preceding
data in the shift register is shifted out the DATA-OUT pin to
the next µPot in the chain or to ground if it is the last µPot in
the chain. The LOAD/SHIFT line goes high once all of the
new data has been shifted into each of its respective regis-
