This product is not recommended for new designs.
LNK403-410/413-420
LinkSwitch-PH
LED Driver IC Family
Single-Stage PFC, Primary-Side Constant Current Control
and TRIAC Dimming/Non-Dimming Options
Product Highlights
Dramatically Simplifies Off-line LED Drivers
•
Single-stage combination of power factor correction and
accurate constant-current (CC) output
•
Enables very long lifetime designs (no electrolytic capacitors)
•
Eliminates optocoupler and all secondary current control
circuitry
•
Eliminates control loop compensation circuitry
•
Simple primary-side PWM dimming interface
•
Universal input voltage range
•
LNK403-410 optimized for flicker-free TRIAC dimming
EcoSmart
™
– Energy Efficient
•
Single-stage PFC combined with output CC control
•
Greatly increases efficiency, >90% achievable
•
Reduces component count
•
No current sense resistors
•
Low standby power remote ON/OFF feature
(<50 mW at 230 VAC)
Accurate and Consistent Performance
•
Compensates for transformer inductance variations
•
Compensates for line input voltage variation
•
Frequency jittering greatly reduces EMI filter size and cost
Advanced Protection and Safety Features
•
Auto-restart for short-circuit protection
•
Open circuit fault detection mode
•
Automatic thermal shutdown restart with hysteresis
•
Meets high voltage creepage requirement between DRAIN and
all other signal pins both on PCB and at package
Green Package
•
Halogen free and ROHS compliant package
Applications
•
Off-line LED driver
RV
AC
IN
D
V
LinkSwitch-PH
BP
CONTROL
S
R
FB
PI-6543-082211
Figure 1.
Typical Application Schematic.
Output Power Table
1,2
R
V
= 2 MW
Product
5
85-132 VAC
Minimum Maximum
Output
Output
Power
3
Power
4
2.5 W
4.5 W
2.5 W
3.8 W
4.5 W
5.5 W
6.8 W
8.0 W
18 W
5.5 W
7.0 W
8.0 W
10 W
13.5 W
20 W
31 W
R
V
= 4 MW
85-308 VAC
Minimum
Maximum
Output
Output
Power
3
Power
4
6.5 W
12 W
6.5 W
8.5 W
10 W
12 W
16 W
18 W
40 W
15 W
18 W
22 W
25 W
35 W
50 W
78 W
LNK403/413E/L
LNK404/414E/L
LNK405/415E/L
LNK406/416E/L
LNK407/417E/L
LNK408/418E/L
LNK409/419E/L
LNK410/420E/L
Description
The LinkSwitch™-PH dramatically simplifies implementation of
LED drivers requiring long lifetime, high efficiency, PF
>0.9,
and
TRIAC dimming capability (LNK403-410). The single-stage
combined power factor and constant-current controller eliminates
a switching stage and the electrolytic bulk capacitor. The
advanced primary-side control used by the LinkSwitch-PH device
provides accurate constant current control while eliminating the
need for an optocoupler and current sensing circuits.
LinkSwitch-PH incorporates a 725 V power FET, a continuous-
mode PWM controller, a high-voltage switched current source for
self biasing, frequency jittering, protection circuitry including
cycle-by-cycle current limit and hysteretic thermal shutdown.
www.power.com
Table 1. Output Power Table.
Notes:
1. Continuous power in an open frame with adequate heat sinking at device local
ambient of 70 °C.
2. Power level calculated on typical LED string voltage with efficiency
>80%.
3. Minimum output power with C
BP
= 10
mF.
4. Maximum output power with C
BP
= 100
mF.
LNK4x3EG C
BP
= 10
mF.
5. Package: eSIP-7C, eSIP-7F.
eSIP-7C (E Package)
Figure 2.
Package Options.
eSIP-7F (L Package)
June 2015
This Product is Covered by Patents and/or Pending Patent Applications.
LNK403-410/413-420
BYPASS (BP)
BYPASS
CAPACITOR
SELECT
SOFT-START
TIMER
FAULT
PRESENT
5.9 V
REGULATOR
DRAIN (D)
HYSTERETIC
THERMAL
SHUTDOWN
-
I
LIM
M
I
AUTO-RESTART
COUNTER
5.9 V
5.0 V
VOLTAGE
MONITOR (V)
1V
STOP
LOGIC
JITTER
CLOCK
OSCILLATOR
3-V
T
UV/OV
LINE
SENSE
-
+
BYPASS PIN
UNDERVOLTAGE
Comparator
FB
OFF
DC
MAX
OCP
+
FEEDBACK (FB)
V
BG
I
V
I
FB
FB
OFF
DC
MAX
PFC/CC
CONTROL
M
I
FEEDBACK
SENSE
REFERENCE (R)
6.4 V
REFERENCE
BLOCK
V
BG
Figure 3.
Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
This pin is the power FET drain connection. It also provides
internal operating current for both start-up and steady-state
operation.
SOURCE (S) Pin:
This pin is the power FET source connection. It is also the
ground reference for the BYPASS, FEEDBACK, REFERENCE and
VOLTAGE MONITOR pins.
BYPASS (BP) Pin:
This is the connection point for an external bypass capacitor for
the internally generated 5.9 V supply. This pin also provides
output power selection through choice of the BYPASS pin
capacitor value.
FEEDBACK (FB) Pin:
The FEEDBACK pin is used for output voltage feedback. The
current into the FEEDBACK pin is directly proportional to the
output voltage. The FEEDBACK pin also includes circuitry to
protect against open load and overload output conditions.
REFERENCE (R) Pin:
This pin is connected to an external precision resistor and is
used to configure for dimming (LNK403-410) and non-TRIAC
dimming (LNK413-420) modes of operation.
VOLTAGE MONITOR (V) Pin:
This pin interfaces with an external input line peak detector,
consisting of a rectifier, filter capacitor and resistors. The
applied current is used to control stop logic for line under-
voltage (UV), overvoltage (OV), provide feed-forward to control
the output current and the remote ON/OFF function.
Exposed Pad
(Backside) Internally
Connected to
SOURCE Pin
E Package (eSIP-7C)
(Top View)
7D
5S
4 BP
3 FB
2V
1R
Exposed Pad
(backside) Internally
Connected to
SOURCE Pin (see
eSIP-7C Package
Drawing)
Figure 4.
Pin Configuration.
2
Rev. G 06/15
+
Gate
Driver
SenseFet
LEB
CURRENT LIMIT
COMPARATOR
-
I
LIM
V
SENSE
I
S
PI-5431-102610
SOURCE (S)
L Package (eSIP-7F)
1 3 5
R FB S
7
Lead Bend Outward
2 4
V BP D
from Drawing
(Refer to eSIP-7F Package
Outline Drawing)
PI-5432-082411
www.power.com
LNK403-410/413-420
Functional Description
A LinkSwitch-PH device monolithically integrates a controller and
high-voltage power FET into one package. The controller
implements both high power factor and a constant current
output in a single stage. The LinkSwitch-PH controller consists
of an oscillator, feedback (sense and logic) circuit, 5.9 V regulator,
hysteretic over-temperature protection, frequency jittering,
cycle-by-cycle current limit, auto-restart, inductance correction,
power factor and constant current control.
FEEDBACK Pin Current Control Characteristics
The figure shown below illustrates the operating boundaries of
the FEEDBACK pin current. Above I
FB(SKIP)
switching is disabled
and below I
FB(AR)
the device enters into auto-restart.
and overvoltage thresholds of the VOLTAGE MONITOR pin. For
non-dimming or PWM dimming applications with LNK413-420,
the external resistor should be a 24.9 kW ±1%, for high-line and
universal input voltage designs, and 49.9 kW ±1% for low-line
input voltage designs. For phase angle AC dimming with
LNK403-410, the external resistor should be a 49.9 kW ±1%.
One percent resistors are recommended as the resistor
tolerance directly affects the output tolerance. Other resistor
values should not be used.
BYPASS Pin Capacitor Power Gain Selection
LinkSwitch-PH devices have the capability to tailor the internal
gain to either full or a reduced output power setting. This allows
selection of a larger device to minimize dissipation for both
thermal and efficiency reasons. The power gain is selected with
the value of the BYPASS pin capacitor. The full power setting is
selected with a 100
mF
capacitor and the reduced power setting
(for higher efficiency) is selected with a 10
mF
capacitor. The
BYPASS pin capacitor sets both the internal power gain as well
as the over-current protection (OCP) threshold. Unlike the
larger devices, the LNK4x3 power gain is not programmable.
Use a 10
mF
capacitor for the LNK4x3.
Switching Frequency
The switching frequency is 66 kHz. To further reduce the EMI
level, the switching frequency is jittered (frequency modulated)
by approximately ±1 kHz.
Soft-Start
The controller includes a soft-start timing feature which inhibits
the auto-restart protection feature for the soft-start period (t
SOFT
)
to distinguish start-up into a fault (short-circuit) from a large
output capacitor. At start-up the LinkSwitch-PH clamps the
maximum duty cycle to reduce the output power. The total
soft-start period is t
SOFT
.
Remote ON/OFF and EcoSmart
The VOLTAGE MONITOR pin has a 1 V threshold comparator
connected at its input. This voltage threshold is used for
remote ON/OFF control. When a signal is received at the
VOLTAGE MONITOR pin to disable the output (VOLTAGE
MONITOR pin tied to ground through an optocoupler photo-
transistor) the LinkSwitch-PH will complete its current switching
cycle before the internal power FET is forced off.
The remote ON/OFF feature can also be used as an eco-mode
or power switch to turn off the LinkSwitch-PH and keep it in a
very low power consumption state for indefinite long periods.
When the LinkSwitch-PH is remotely turned on after entering
this mode, it will initiate a normal start-up sequence with
soft-start the next time the BYPASS pin reaches 5.9 V. In the
worst case, the delay from remote on to start-up can be equal
to the full discharge/charge cycle time of the BYPASS pin. This
reduced consumption remote off mode can eliminate expensive
and unreliable in-line mechanical switches.
I
FB(SKIP)
Skip-Cycle
I
FB
CC Control
Region
I
FB(DCMAXR)
Soft-Start and
CC Fold-Back
Region
I
FB(AR)
DC10
Auto-Restart
DC
MAX
PI-5433-060410
Maximum Duty Cycle
Figure 5.
FEEDBACK Pin Current Characteristic.
The FEEDBACK pin current is also used to clamp the maximum
duty cycle to limit the available output power for overload and
open-loop conditions. This duty cycle reduction characteristic
also promotes a monotonic output current start-up characteristic
to prevent over-shoot.
REFERENCE Pin
The REFERENCE pin is tied to ground (SOURCE) via an external
resistor. The value selected sets the internal references,
determining the operating mode for dimming (LNK403-410) and
non-dimming (LNK413-420) operation and the line undervoltage
3
www.power.com
Rev. G 06/15
LNK403-410/413-420
Over-Current Protection
The current limit circuit senses the current in the power FET.
When this current exceeds the internal threshold (I
LIMIT
), the power
FET is turned off for the remainder of that cycle. A leading edge
blanking circuit inhibits the current limit comparator for a short
time (t
LEB
) after the power FET is turned on. This leading edge
blanking time has been set so that current spikes caused by
capacitance and rectifier reverse recovery will not cause
premature termination of the power FET conduction.
Line Under/Overvoltage Protection
This device includes both line under- and overvoltage detection
to limit the minimum start-up and maximum operating voltage
detected through the VOLTAGE MONITOR pin. An external peak
detector consisting of a diode and capacitor are required to
provide input line peak voltage to the VOLTAGE MONITOR pin
through a resistor. At power up, I
UV+
keeps the LinkSwitch-PH
off until the input line voltage reaches the undervoltage threshold.
At power down, I
UV-
prevents restart attempts after the output
goes out of regulation.
The same resistor used for UV also sets line overvoltage (OV)
shutdown threshold which, once exceeded, forces the
LinkSwitch-PH to stop switching (after completion of the current
switching cycle). Once the line voltage returns to normal, the
device resumes normal operation. A small amount of hysteresis
is provided on the OV threshold to prevent noise triggering.
When the power FET is off, the rectified DC high voltage surge
capability is increased to the voltage rating of the power FET
(725 V), due to the absence of the reflected voltage and leakage
spikes on the drain.
Hysteretic Thermal Shutdown
The thermal shutdown circuitry senses the controller die
temperature. The threshold is set at 142 °C typical with a 75 °C
hysteresis. When the die temperature rises above this threshold
(142 °C) the power FET is disabled and remains disabled until
the die temperature falls by 75 °C, at which point the power FET
is re-enabled.
Safe Operating Area (SOA) Protection
The device also features a safe operating area (SOA) protection
mode which disables FET switching for 40 cycles in the event
the peak switch current reaches the I
LIMIT
threshold and the
switch on-time is less than t
ON(SOA)
. This protection mode protects
the device under short-circuited LED conditions and at start-up
during the soft-start period when auto-restart protection is inhibited.
The SOA protection mode remains active in normal operation.
D
V
CONTROL
BP
S
R
FB
PI-5435-052510
Figure 6.
Remote ON/OFF VOLTAGE MONITOR pin Control
5.9 V Regulator/Shunt Voltage Clamp
The internal 5.9 V regulator charges the bypass capacitor
connected to the BYPASS pin to 5.9 V by drawing a current
from the voltage on the DRAIN pin whenever the power FET is
off. The BYPASS pin is the internal supply voltage node. When
the power FET is on, the device operates from the energy
stored in the bypass capacitor. Extremely low power
consumption of the internal circuitry allows LinkSwitch-PH
to operate continuously from current it takes from the DRAIN
pin. A bypass capacitor value of 10 or 100
mF
is sufficient for
both high frequency decoupling and energy storage. In
addition, there is a 6.4 V shunt regulator clamping the BYPASS
pin at 6.4 V when current is provided to the BYPASS pin
through an external resistor. This facilitates powering of
LinkSwitch-PH externally through a bias winding to increase
operating efficiency. It is recommended that the BYPASS pin is
supplied current from the bias winding for normal operation.
Auto-Restart
In the event of an open-loop fault (open FEEDBACK pin resistor
or broken path to feedback winding), output short-circuits or an
overload condition the controller enters into the auto-restart
mode. The controller annunciates both short-circuit and
open-loop conditions once the FEEDBACK pin current falls
below the I
FB(AR)
threshold after the soft-start period. To
minimize the power dissipation under this fault condition the
shutdown/auto-restart circuit turns the power supply on (same
as the soft-start period) and off at an auto-restart duty cycle of
typically DC
AR
for as long as the fault condition persists. If the
fault is removed during the auto-restart off-time, the power
supply will remain in auto-restart until the full off-time count is
completed. Special consideration must be made to appropriately
size the output capacitor to ensure that after the soft-start
period (t
SOFT
) the FEEDBACK pin current is above the I
FB(AR)
threshold to ensure successful power-supply start-up.
After the soft-start time period, auto-restart is activated only
when the FEEDBACK pin current falls below I
FB(AR)
.
4
Rev. G 06/15
www.power.com
LNK403-410/413-420
Application Example
14 W TRIAC Dimmable High Power Factor LED Driver
Design Example
The circuit schematic in Figure 7 shows a TRIAC dimmable high
power-factor LED driver based on LNK406EG from the
LinkSwitch-PH family of devices. It was optimized to drive an
LED string at a voltage of 28 V with a constant current of 0.5 A
(±5%) ideal for PAR lamp retro-fit applications. The design
operates over a universal input voltage range of 90 VAC to
265 VAC but provides the specified output current tolerance
over a line voltage range of 90 VAC to 132 VAC (this is configurable
for high-line only applications by simple component value changes).
The key goals of this design were compatibility with standard
leading edge TRIAC AC dimmers, very wide dimming range
(1000:1, 500 mA:0.5 mA), high efficiency (>85%) and high power
factor (>0.9). The design is fully protected from faults such as
no-load, overload and output short-circuit conditions and over
temperature.
Circuit Description
The LinkSwitch-PH device (U1) integrates the power FET,
controller and start-up functions into a single package reducing
the component count versus typical implementations. Configured
as part of an isolated continuous conduction mode flyback
converter, U1 provides high power factor via its internal control
algorithm together with the small input capacitance of the
design. Continuous conduction mode operation results in
reduced primary peak and RMS current. This both reduces
EMI noise, allowing simpler, smaller EMI filtering components and
improves efficiency. Output current regulation is maintained
without the need for secondary-side sensing which eliminates
current sense resistors and improves efficiency.
Input Stage
Fuse F1 provides protection from component failures while RV1
provides a clamp during differential line surges, keeping the
peak drain voltage of U1 below the 725 V rating of the internal
power FET. Bridge rectifier BR1 rectifies the AC line voltage.
EMI filtering is provided by L1-L3, C1, R16 and R17 together with
the safety rated Y class capacitor (C7) that bridges the safety
isolation barrier between primary and secondary. Resistor R16
and R17 act to damp any resonances formed between L1, L2,
C1 and the AC line impedance. A small bulk capacitor (C2) is
required to provide a low impedance source for the primary
switching current. The maximum value of C1 and C2 is limited in
order to maintain a power factor of greater than 0.9.
LinkSwitch-PH Primary
To provide peak line voltage information to U1 the incoming
rectified AC peak charges C3 via D2. This is then fed into the
VOLTAGE MONITOR pin of U1 as a current via R2 and R3. This
sensed current is also used by the device to set the line input
overvoltage and undervoltage protection thresholds. Resistor
R1 provides a discharge path for C3 with a time constant much
longer than that of the rectified AC to prevent generation of line
frequency ripple.
The VOLTAGE MONITOR pin current and the FEEDBACK pin
current are used internally to control the average output LED
current. For TRIAC phase-dimming applications a 49.9 kW
resistor (R4) is used on the REFERENCE pin and 4 MW (R2+R3)
on the VOLTAGE MONITOR pin to provide a linear relationship
between input voltage and the output current and maximizing
the dimming range. Resistor R4 also sets the internal line input
undervoltage and overvoltage protection thresholds.
11
FL1
C8
C10
330
µF
330
µF
R15
50 V
50 V 20 kΩ
D8
MBRS4201T3G
28 V, 500 mA
L3
1000
µH
R9
750 kΩ
1%
R18
510
Ω
1W
R16
1 kΩ
L
F1
3.15 A
L1
1000
µH
90 - 265
VAC
RV1
275 VAC
C1
47 nF
275 VAC
C11
220 nF
630 V
C2
100 nF
630 V
BR1
2KBP06M
600 V
R10
750 kΩ
1%
R2
2 MΩ
1%
R3
2 MΩ
1%
C3
1
µF
400 V
D
V
CONTROL
R1
240 kΩ
1/2 W
D2
DL4007
VR1
P6KE200A
D3
UF4007
1
FL2
3
RTN
R8
D6
150
Ω
DL4936
R7
10 kΩ
C5
22
µF
50 V
2
T1
RM8
D4
UF4002
D5
1N4148
R5
3 kΩ
BP
L2
1000
µH
N
R17
1 kΩ
D1
DL4002
VR2
ZMM5245B-7
15 V
R12
15
Ω
1%
LinkSwitch-PH
U1
LNK406EG
S
R6
162 kΩ
1%
VR3
ZMM5259B-7
39 V
D7
BAV21WS-7-F
R
FB
R11
2.4 MΩ
Q1
FMMT558
C6
15 nF
50 V
Q2
IRFR310
R13
130
Ω
1/2 W
Q3
MMBT3904
C13
100 nF
50 V
R4
49.9 kΩ
C4
1%
10
µF
16 V
R19
1 kΩ
R20
10 kΩ
C12
1
µF
50 V
C7
2.2 nF
250 VAC
PI-5997-061510
Figure 7.
Schematic of an Isolated, TRIAC Dimmable, High Power Factor, Universal Input, 14 W LED Driver.
5
www.power.com
Rev. G 06/15
FPGA/CPLD
