LT3462/LT3462A
Inverting 1.2MHz/2.7MHz
DC/DC Converters with
Integrated Schottky in ThinSOT
FEATURES
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DESCRIPTIO
Integrated Schottky Rectifier
Fixed Frequency 1.2MHz/2.7MHz Operation
Very Low Noise: 1mV
P-P
Output Ripple
Low V
CESAT
Switch: 270mV at 250mA
–5V at 100mA from 5V Input
–12V at 30mA from 3.3V Input
Low Input Bias Current GND Based FB Input
Low Impedance (40Ω) 1.265V Reference Output
High Output Voltage: Up to – 38V
Wide Input Range: 2.5V to 16V
Uses Tiny Surface Mount Components
Low Shutdown Current: <10µA
Low Profile (1mm) SOT-23 (ThinSOT
TM
) Package
The LT
®
3462/LT3462A are general purpose fixed fre-
quency current mode inverting DC/DC converters. Both
devices feature an integrated Schottky and a low V
CESAT
switch allowing a small converter footprint and lower parts
cost. The LT3462 switches at 1.2MHz while the LT3462A
switches at 2.7MHz. These high speeds enable the use of
tiny, low cost and low height capacitors and inductors.
The LT3462/LT3462A operate in a dual inductor inverting
topology that filters both the input and output currents.
Very low output voltage ripple approaching 1mV
P-P
can be
achieved when ceramic capacitors are used. Fixed fre-
quency switching ensures a clean output free from low
frequency noise typically present with charge pump solu-
tions. The 40V switch allows a V
IN
to V
OUT
differential of
up to 38V for dual inductor topologies.
Both devices provide a low impedance 1.265V reference
output to supply the feedback resistor network. A ground
referenced, high impedance FB input allows high feedback
resistor values without compromising output accuracy.
The LT3462/LT3462A are available in a 6-lead SOT-23
package.
APPLICATIO S
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CCD Bias
LCD Bias
GaAs FET Bias
General Purpose Negative Voltage Supply
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation
TYPICAL APPLICATIO
22µH
1µF
5V to –5V, 100mA Inverting DC/DC Converter
75
22µH
V
IN
5V
T
A
= 25°C
1µF
SW
V
IN
D
FB
267k
22pF
EFFICIENCY (%)
V
OUT
–5V
100mA
70
V
IN
= 3.3V
65
LT3462A
SDREF
GND
68.1k
10µF
60
3462 TA01
55
0
20
U
Efficiency
V
IN
= 5V
60
80
40
LOAD CURRENT (mA)
100
3462 TA01b
U
U
3462af
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LT3462/LT3462A
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
SW 1
GND 2
FB 3
6 V
IN
5D
4 SDREF
Input Voltage (V
IN
) .................................................. 16V
SW Voltage .............................................................. 40V
D Voltage ............................................................... –40V
SDREF, FB Voltage ................................................. 2.5V
Operating Ambient
Temperature Range (Note 3) ...............–40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10sec)................... 300°C
ORDER PART
NUMBER
LT3462ES6
LT3462AES6
S6 PART MARKING
LTBBV
LTBGB
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
T
JMAX
= 125°C
θ
JA
= 150°C ON BOARD OVER
GROUND PLANE
θ
JC
= 120°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C, V
IN
= 3V, unless otherwise noted.
PARAMETER
Minimum Operating Voltage
Maximum Operating Voltage
SDREF Voltage
FB Pin Bias Current (Note 2)
SDREF Minus FB Voltage
Error Amp Offset Voltage
SDREF Reference Source Current
Supply Current
SDREF Line Regulation
Switching Frequency (LT3462)
Switching Frequency (LT3462A)
Maximum Duty Cycle (LT3462)
Maximum Duty Cycle (LT3462A)
Switch Current Limit
Switch V
CESAT
Switch Leakage Current
Rectifier Leakage Current
Rectifier Forward Drop
SDREF Voltage Low
SDREF Off-State Pull-Up Current
SDREF Turn-Off Current
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Current flows out of the pin.
I
SW
= 250mA
V
SW
= 5V
V
D
= –40V
I
SCHOTTKY
= 250mA
q
q
q
q
q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
2.5
TYP
MAX
16
UNITS
V
V
V
nA
V
mV
µA
mA
µA
%/V
MHz
MHz
%
%
10µA > I
SDREF
≥
–80µA
10µA > I
SDREF
≥
–80µA
SDREF >1.2V
FB = –0.05V, Not Switching
SDREF = 0V, FB = Open, V
IN
= 5V
q
1.245
1.235
–12
120
1.265
15
1.263
180
2.9
6.5
0.007
1.285
50
1.285
12
3.6
10
1.6
3.5
q
q
0.8
2.0
90
77
300
1.2
2.7
420
270
0.01
0.03
800
350
1
4
1100
0.20
3
1
–300
2
–200
Note 3:
The LT3462E is guaranteed to meet specifications from 0°C to
70°C. Specifications over the –40°C to 85°C operating temperature range
are assured by design, characterization and correlation with statistical
process controls.
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mA
mV
µA
µA
mV
V
µA
µA
W
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W W
W
LT3462/LT3462A
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency (LT3462)
1.6
1.5
CURRENT LIMIT (mA)
360
LT3462A
FREQUENCY (MHz)
1.4
1.3
1.2
1.1
1.0
–40 –20
0
10
480
T
A
= 25°C
LT3462
SDREF MINUS FB (V)
1.28
1.27
1.26
1.25
1.24
1.23
–40 –20
40
20
60
0
TEMPERATURE (°C)
Oscillator Frequency (LT3462A)
3.2
T
A
= 25°C
3.0
FB BIAS CURRENT (nA)
FREQUENCY (MHz)
2.8
2.6
2.4
2.2
2.0
–40 –20
0
–5
–15
–20
–25
–30
–35
–40
–45
QUIESCENT CURRENT (µA)
40
20
60
0
TEMPERATURE (°C)
PI FU CTIO S
SW (Pin 1):
Switch Pin. Connect to external inductor L1
and positive terminal of transfer cap.
GND (Pin 2):
Ground. Tie directly to local ground plane.
FB (Pin 3):
Feedback Pin. Connect resistive divider tap
here. Set R1 according to R1 = R2 • (V
OUT
/1.265V). In
shutdown, a proprietary shutdown bias current cancella-
tion circuit allows the internal 3µA source to pull up the
SDREF pin, even with residual negative voltage on V
OUT
.
SDREF (Pin 4):
Dual Function Shutdown and 1.265V
Reference Output Pin. Pull to GND with external N-FET to
turn regulator off. Turn-off pull-down and a 2µA internal
source will pull SDREF up to turn-on the regulator. At turn-
on, a 180µA internal source pulls the pin to the regulation
voltage. The SDREF pin can supply up to 80µA at 1.265V
to bias the feedback resistor divider. An optional soft-start
circuit capacitor connects from this pin to –V
OUT
.
D (Pin 5):
Anode Terminal of Integrated Schottky Diode.
Connect to negative terminal of transfer cap and external
inductor L2.
V
IN
(Pin 6):
Input Supply Pin. Must be locally bypassed.
3462af
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80
100
3462 G01
Current Limit
1.29
SDREF Minus FB Pin Voltage
240
120
20
30
40 50 60 70
DUTY CYCLE (%)
80
90
40
20
60
0
TEMPERATURE (°C)
80
100
3462 G02
3462 G03
FB Bias Current
10
Quiescent Current in
Shutdown Mode
T
A
= 25°C
FB = N/C
8
–10
6
4
2
80
100
–50
–40
0
–20
0
20
40
60
TEMPERATURE (°C)
80
100
3462 G05
0
4
8
12
16
3462 G06
SUPPLY VOLTAGE (V)
3462 G04
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3
LT3462/LT3462A
BLOCK DIAGRA
FB 3
SDREF 4
SHUTDOWN
BIAS CURRENT
CANCELLATION
OFF
→
3µA
ON
→
180µA
SHUTDOWN
V
IN
6
1.265V
REFERENCE
OPERATIO
The LT3462 uses a constant frequency, current mode
control scheme to provide excellent line and load regula-
tion. Operation can be best understood by referring to the
Block Diagram in Figure 1. At the start of each oscillator
cycle, the SR latch is set, turning on the power switch Q1.
A voltage proportional to the switch current is added to a
stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator. When this
voltage exceeds the voltage at the output of the EAMP, the
SR latch is reset, turning off the power switch. The level
at the output of the EAMP is simply an amplified version
of the difference between the feedback voltage and GND.
In this manner, the error amplifier sets the correct peak
current level to keep the output in regulation. If the error
amplifier’s output increases, more current is taken from
the output; if it decreases, less current is taken. One
function not shown in Figure 1 is the current limit. The
switch current is constantly monitored and not allowed to
exceed the nominal value of 400mA. If the switch current
reaches 400mA, the SR latch is reset regardless of the
4
W
1
SW
5 D
–
A1
E AMP
–
R
C
C
C
A2
COMP
R
S
Q
DRIVER
Q1
DO
LG
+
+
∑
+
0.1Ω
ISRC
RAMP
GENERATOR
V
OUT
1.2MHz*
OSCILLATOR
*LT3462A IS 2.7MHz
R1 (EXTERNAL)
FB
R2 (EXTERNAL)
Q2
SDREF
C
S1
, C
S2
OPTIONAL SOFT-START COMPONENTS
3462 F02
–
2 GND
V
OUT
C
S1
(EXTERNAL)
SDREF
C
S2
(EXTERNAL)
–
+
Figure 1. Block Diagram
U
output state of the PWM comparator. This current limit cell
protects the power switch as well as various external
components connected to the LT3462.
SDREF is a dual function input pin. When driven low it
shuts the part down, reducing quiescent supply current to
less than 10µA. When not driven low, the SDREF pin has an
internal pull-up current that turns the regulator on. Once
the part is enabled, the SDREF pin sources up to
180µA nominally at a fixed voltage of 1.265V through
external resistor R2 to FB. If there is no fault condition
present, FB will regulate to 0V, and V
OUT
will regulate to
1.265V • (–R1/R2). An optional soft-start circuit uses the
fixed SDREF pull-up current and a capacitor from SDREF
to V
OUT
to set the dV/dt on V
OUT
. In shutdown, an FB bias
current cancellation circuit supplies up to 150µA biasing
current to external resistor R1 while V
OUT
is lower than FB.
This function eliminates R2 loading of SDREF during
shutdown. As a result, supply current in shutdown may
exceed 10µA by the amount of current flowing in R1.
3462af
LT3462/LT3462A
APPLICATIO S I FOR ATIO
Inrush Current
The LT3462 has a built-in Schottky diode. When supply
voltage is applied to the V
IN
pin, the voltage difference
between V
IN
and V
D
generates inrush current flowing from
input through the inductor and the Schottky diode to
charge the flying capacitor to V
IN
. The maximum
nonrepetitive surge current the Schottky diode in the
LT3462 can sustain is 1.5A. The selection of inductor and
capacitor value should ensure the peak of the inrush
current to be below 1.5A. The peak inrush current can be
calculated as follows:
π
V
IN
– O.6
exp
–
I
P
=
L
L
–1
2
– 1
C
C
where L is the inductance between supply and SW, and C
is the capacitance between SW and D.
Table 3 gives inrush peak currents for some component
selections.
Table 3. Inrush Peak Current
V
IN
(V)
5
5
12
L (µH)
22
33
47
C (µF)
1
1
1
I
P
(A)
0.70
0.60
1.40
Inductor Selection
Each of the two inductors used with LT3462 should have
a saturation current rating (where inductance is approxi-
mately 70% of zero current inductance ) of approximately
0.25A or greater. If the device is used in the charge pump
mode, where there is only one inductor, then its rating
should be 0.35A or greater. DCR of the inductors should
be less than 1Ω. For LT3462, a value of 22µH is suitable
if using a coupled inductor such as Sumida CLS62-220. If
using two separate inductors, increasing the value to
47µH will result in the same ripple current. For LT3462A,
a value of 10µH for the coupled inductor and 22µH for two
inductors will be acceptable for most applications.
C3
R1
U
Capacitor Selection
Ceramic capacitors are recommended. An X7R or X5R
dielectric should be used to avoid capacitance decreasing
severely with applied voltage and at temperature limits.
The “flying” capacitor between the SW and D pins should
be a ceramic type of value 1µF or more. When used in the
dual inductor or coupled inductor topologies the flying
capacitor should have a voltage rating that is more than the
difference between the input and output voltages. For the
charge pump inverter topology, the voltage rating should
be more than the output voltage. The output capacitor
should be a ceramic type. Acceptable output capacitance
varies from 1µF for high V
OUT
(–36V), to 10µF for low V
OUT
(–5V). The input capacitor should be a 1µF ceramic type
and be placed as close as possible to the LT3462/LT3462A.
Layout Hints
The high speed operation of the LT3462 demands careful
attention to board layout. You will not get advertised
performance with careless layout. Figure 2 shows the
recommended component placement. A ceramic capaci-
tor of 1µF or more must be placed close to the IC for input
supply bypassing.
C1
W
U U
+
GND
L1
V
IN
1
2
3
R2
6
5
4
L2
C2
C4
V
OUT
3462 F03
Figure 2. Suggested Layout
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