ESMT
Revision History
Revision 0.1 (15 Jan. 2002)
-
Original
Revision 0.2 (19 Nov. 2002)
-changed ordering information & DC/AC characteristics
Revision 0.1
M13S128168A - 5T
M13S128168A - 6T
Revision 0.2
M13S128168A - 6T
M13S128168A - 7.5AB
M13S128168A
Revision 0.3 (8 Aug. 2003)
-Change IDD6 from 3mA to 5mA.
Revision 0.4 (27 Aug. 2003)
-Change ordering information & DC / AC characteristics.
Revision 1.0 (21 Oct. 2003)
-Modify tWTR from 2tck to 1tck.
Revision 1.1 (10 Nov. 2003)
-Correct some refresh interval that is not revised.
-Correct some CAS Lantency that is not revised.
Revision 1.2 (12 Jan. 2004)
-Correct IDD1; IDD4R and IDD4W test condition.
-Correct tRCD; tRP unit
-Add tCCD spec.
-Add tDAL spec.
Revision 1.3 (12 Mar. 2004)
-Add Cas Latency=2; 2.5
Revision 1.4 (23 Jun. 2005)
-Add Pb-free to ordering information
-Modify IDD0 and IDD1 spec
-Modify some AC timing unit from tCK to ns.
Revision 1.5 (29 May. 2006)
-Delete CL2 ; CL2.5
-Modify tREFI
-Delete Non-pb-free form ordering information
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2006
Revision : 1.5
1/48
ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.375V ~ 2.75V, V
DDQ
= 2.375V ~ 2.75V
Auto & Self refresh
15.6us refresh interval (64ms refresh period, 4K cycle)
SSTL-2 I/O interface
66pin TSOPII package
M13S128168A
2M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Ordering information :
PRODUCT NO.
M13S128168A -5TG
M13S128168A -6TG
MAX FREQ
200MHz
166MHz
VDD
2.5V
PACKAGE
TSOPII
COMMENTS
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2006
Revision : 1.5
2/48
ESMT
Functional Block Diagram
CLK
CLK
CKE
Address
Mode Register &
Extended Mode
Register
M13S128168A
Clock
Generator
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DM
Column Decoder
DQ
CLK, CLK
DLL
DQS
DQS
Pin Arrangement
x16
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CLK
CLK
CKE
NC
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2006
Revision : 1.5
3/48
ESMT
Pin Description
(M13S128168A)
Pin Name
Function
Address inputs
- Row address A0~A11
- Column address A0~A8
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
Pin Name
M13S128168A
Function
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL-2
A0~A11,
BA0,BA1
LDM, UDM
DQ0~DQ15
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
V
SS
V
DD
LDQS, UDQS
NC
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2006
Revision : 1.5
4/48
ESMT
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note :
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
TBD
50
M13S128168A
Unit
V
V
V
°C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= 0 to 70 °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
Output Low Current (Normal strength driver)
(V
OUT
= 0.373V)
Output High Current (Weak strength driver)
(V
OUT
=V
DDQ
-0.763V, min V
REF
, min V
TT
)
Output Low Current (Weak strength driver)
(V
OUT
= 0.763V)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
I
I
I
OZ
I
OH
I
OL
I
OH
I
OL
Min
2.375
2.375
0.49*V
DDQ
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
-5
-5
-16.8
+16.8
-9
+9
Max
2.75
2.75
0.51*V
DDQ
V
REF
+ 0.04
V
DDQ
+ 0.3
V
REF
- 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
5
5
Unit
V
V
V
V
V
V
V
V
1
2
Note
μ
A
μ
A
mA
mA
mA
mA
3
Notes 1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2. V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set equal
to V
REF
, and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2006
Revision : 1.5
5/48
