M24C64
M24C32
64/32 Kbit Serial I²C Bus EEPROM
s
s
Compatible with I
2
C Extended Addressing
Two Wire I
2
C Serial Interface
Supports 400 kHz Protocol
Single Supply Voltage:
– 4.5V to 5.5V for M24Cxx
– 2.5V to 5.5V for M24Cxx-W
– 1.8V to 3.6V for M24Cxx-R
s
8
1
PSDIP8 (BN)
0.25 mm frame
14
1
TSSOP14 (DL)
169 mil width
s
s
s
s
s
s
s
s
Hardware Write Control
BYTE and PAGE WRITE (up to 32 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behaviour
1 Million Erase/Write Cycles (minimum)
40 Year Data Retention (minimum)
8
1
SO8 (MN)
150 mil width
8
1
SO8 (MW)
200 mil width
DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are fabricated with STMi-
croelectronics’
High
Endurance,
Single
Polysilicon, CMOS technology. This guarantees
an endurance typically well above one million
Erase/Write cycles, with a data retention of
40 years. The memories are organised as 8192x8
bits (M24C64) and 4096x8 bits (M24C32), and op-
erate down to 2.5 V (for the -W version of each de-
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
E0, E1, E2
SDA
Chip Enable Inputs
Serial Data/Address Input/
Output
Serial Clock
Write Control
Supply Voltage
Ground
3
E0-E2
SCL
WC
M24C64
M24C32
SDA
SCL
WC
V
CC
V
SS
VSS
AI01844B
January 1999
1/18
M24C64, M24C32
Figure 2A. DIP Connections
Figure 2C. TSSOP Connections
M24C64
M24C32
E0
E1
NC
NC
NC
E2
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
AI02129
M24C64
M24C32
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI01845B
VCC
WC
SCL
SDA
VCC
WC
NC
NC
NC
SCL
SDA
Note: 1. NC = Not Connected
Figure 2B. SO Connections
M24C64
M24C32
E0
E1
E2
VSS
1
2
3
4
8
7
6
5
AI01846B
VCC
WC
SCL
SDA
vice), and down to 1.8 V (for the -R version of each
device).
The M24C64 and M24C32 are available in Plastic
Dual-in-Line, Plastic Small Outline and Thin Shrink
Small Outline packages.
These memory devices are compatible with the
I
2
C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I
2
C bus definition.
The memory behaves as a slave device in the I
2
C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Table 2. Absolute Maximum Ratings
1
Symbol
T
A
T
STG
T
LEAD
V
IO
V
CC
V
ESD
Electrostatic Discharge Voltage (Machine model)
3
500
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500
Ω)
3. EIAJ IC-121 (Condition C) (200 pF, 0
Ω)
Parameter
Ambient Operating Temperature
Storage Temperature
Lead Temperature during Soldering
Input or Output range
Supply Voltage
Electrostatic Discharge Voltage (Human Body model)
2
PSDIP8: 10 sec
SO8: 40 sec
TSSOP14: t.b.c.
Value
-40 to 125
-65 to 150
260
215
t.b.c.
-0.6 to 6.5
-0.3 to 6.5
4000
Unit
°C
°C
°C
V
V
V
2/18
M24C64, M24C32
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the V
CC
voltage has reached the
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when V
CC
drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
the SCL line to V
CC
. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V
CC
. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)
These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs may be driven dynamically or tied to
V
CC
or V
SS
to establish the device select code (but
note that the V
IL
and V
IH
levels for the inputs are
CMOS compatible, not TTL compatible).
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=V
IL
) or disable (WC=V
IH
)
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
V
IL
, and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note
AN404
for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I
2
C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001
. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
VCC
20
Maximum RP value (kΩ)
16
RL
12
8
4
0
10
100
CBUS (pF)
AI01665
RL
SDA
MASTER
fc = 100kHz
fc = 400kHz
SCL
CBUS
CBUS
1000
3/18
M24C64, M24C32
Figure 4. I
2
C Bus Protocol
SCL
SDA
START
CONDITION
SDA
INPUT
SDA
CHANGE
STOP
CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START
CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP
CONDITION
AI00792
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica-
tion.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9
th
clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change
only
when the SCL
line is low.
4/18
M24C64, M24C32
Table 3. Device Select Code
1
Device Type Identifier
b7
Device Select Code
1
b6
0
b5
1
b4
0
b3
E2
Chip Enable
b2
E1
b1
E0
RW
b0
RW
Note: 1. The most significant bit, b7, is sent first.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a sin-
gle I
2
C bus. Each one is given a unique 3-bit code
on its Chip Enable inputs. When the Device Se-
lect Code is received on the SDA bus, the memory
only responds if the Chip Select Code is the same
as the pattern applied to its Chip Enable pins.
The 8
th
bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9
th
bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4) is sent first, followed by the Least significant
Table 4. Most Significant Byte
b15
b14
b13
b12
b11
b10
b9
b8
Note: 1. b15 to b13 are Don’t Care on the M24C64 series.
b15 to b12 are Don’t Care on the M24C32 series.
Table 5. Least Significant Byte
b7
b6
b5
b4
b3
b2
b1
b0
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory. Bits b15 to b13 are treated as
a Don’t Care bit on the M24C64 memory. Bits b15
to b12 are treated as Don’t Care bits on the
M24C32 memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will
not
be acknowledged
(as shown in Figure 5).
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
Table 6. Operating Modes
Mode
Current Address Read
Random Address Read
‘1’
Sequential Read
Byte Write
Page Write
Note: 1. X =
V
IH
or V
IL
.
RW bit
‘1’
‘0’
WC
1
X
X
Bytes
1
1
Initial Sequence
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
X
X
V
IL
V
IL
≥
1
1
≤
32
‘1’
‘0’
‘0’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
5/18
