• Apply 4.15 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to the Vcc pin. Apply 0 V to the
Vss pin.
• This controls the MCU operating mode. Connect this pin to Vss. If connecting this pin to Vcc, the
internal ROM is inhibited. In the flash memory version this pin functions as a V
PP
power supply input pin.
• These pins are the power supply inputs for analog circuitry.
• Reset input pin for active “L.”
• Connect a ceramic resonator or a quartz-crystal oscillator between the X
IN
and X
OUT
pins to set the
oscillation frequency.
• If an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
• Loop filter for the frequency synthesizer.
• It is a capacitor connection pin for built-in DC-DC converter. At Vcc=5 V, use built-in DC-DC converter
by permitting a USB line driver and connect a capacitor. Refer to "Notes on use" for details. Built-in DC-
DC converter cannot be used at Vcc = 3.3 V. Supply 3.3V power supply to this pin from the externals.
• USB D+ voltage signal port. Connect a 27 to 33
Ω
(recommended) resistor in series.
• USB D- voltage signal port. Connect a 27 to 33
Ω
(recommended) resistor in series.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• When connecting an external memory, these function as the address bus.
I/O port P0
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• When connecting an external memory, these function as the address bus.
• 8-bit I/O port.
• CMOS compatible input level or VIHL input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When connecting an external memory, these function as
the data bus.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When connecting an external memory, these function as
the control bus.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When connecting an external memory, these function as
the control bus.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When enabling the Master CPU bus interface function,
CMOS or TTL input level can be selected as an input.
• Key-on wake-up interrupt input pin
Function
USB D+
USB D-
P0
0
/AB
0
–
P0
7
/AB
7
P1
0
/AB
8
–
P1
7
/AB
15
P2
0
/DB
0
–
P2
7
/DB
7
I/O port P1
P3
0
/RDY,
I/O port P2
P3
1
, P3
2
,
I/O port P3
P3
3
/DMA
OUT
,
P3
4
/φ
OUT
,
P3
5
/SYNC
OUT
,
P3
6
/WR,
P3
7
/RD
P4
0
/EDMA,
(See Remarks.)
P4
1
/INT
0
,
P4
2
/INT
1
,
P4
3
/CNTR
0
,
P4
4
/CNTR
1
P5
0
/X
CIN
,
P5
1
/T
OUT
/
X
COUT
,
P5
2
/OBF
0
,
P5
3
/IBF
0
,
P5
4
/S
0
,
P5
5
/A
0
,
P5
6
/R(E),
P5
7
/W(R/W)
I/O port P4
• External memory control pin
• External memory control pin
• External interrupt pin
• Timer X, Timer Y pin
• Sub-clock generating input pin
• Timers 1, 2 pulse output pins
• Sub-clock generating output pin
• Master CPU bus interface pin
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 4 of 135
7641 Group
Table 2 Pin description (2)
Pin
P6
0
/DQ
0
–
P6
7
/DQ
7
Name
I/O port P5
Function
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When enabling the bus interface function, CMOS or TTL
input level can be selected as its input.
• 5-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
Function except a port function
• Master CPU bus interface pin
P7
0
/SOF,
P7
1
/HOLD,
P7
2
/S
1
,
P7
3
/IBF
1
/
HLDA,
P7
4
/OBF
1
P8
0
/UTXD
2
/
SRDY,
P8
1
/URXD
2
/
SCLK,
P8
2
/CTS
2
/
SRXD,
P8
3
/RTS
2
/
STXD,
P8
4
/UTXD
1
,
P8
5
/URXD
1
,
P8
6
/CTS
1
,
P8
7
/RTS
1
I/O port P6
• USB function pin
• Master CPU bus interface pin
I/O port P7
I/O port P8
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually pro-
grammed as either input or output.
• Serial I/O pin
• UART2 pin
• UART1 pin
Remarks
•DMA
OUT
pin
If externally detecting the timing of DMA execution, use the signal from this pin. It is “H” level during DMA transferring. This signal is valid in the memory expansion
and microprocessor modes.
•SYNC
OUT
pin
If externally detecting the timing of OP code fetch, use the signal from this pin. This signal is valid in the memory expansion and microprocessor modes.
