M87C51FB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH
16 KBYTES USER PROGRAMMABLE EPROM
Military
M87C51FB
3 5 MHz to 12 MHz V
CC
e
5V
g
20%
M87C51FB-16 3 5 MHz to 16 MHz V
CC
e
5V
g
20%
High Performance CHMOS EPROM
Three 16-Bit Timer Counters
Programmable Counter Array with
High Speed Output
Compare Capture
Pulse Width Modulator
Watchdog Timer capabilities
Up Down Timer Counter
Three Level Program Lock System
16K On-Chip EPROM
256 Bytes of On-Chip Data RAM
Improved Quick Pulse Programming
Algorithm
Boolean Processor
ONCE (On-Circuit Emulation) Mode
Available in 40-pin CERDIP and
44-pin Leadless Chip Carrier Packages
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Gullwing and J-lead Packages Also
Available
32 Programmable I O Lines
7 Interrupt Sources
Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
TTL and CMOS Compatible Logic
Levels
64K External Program Memory Space
64K External Data Memory Space
MCS 51 Microcontroller Fully
Compatible Instruction Set
Power Saving Idle and Power Down
Modes
Military Temperature Range
b
55 C to
a
125 C (T
C
)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
MEMORY ORGANIZATION
PROGRAM MEMORY Up to 16 Kbytes of the program memory can reside in the on-chip EPROM In addition
the device can address up to 64K of program memory external to the chip
DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of
external data memory
The Intel M87C51FB is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable
CHMOS III-E technology Being a member of the MCS 51 family of microcontrollers the M87C51FB uses the
same powerful instruction set has the same architecture and is pin-for-pin compatible with the existing
MCS 51 microcontroller family of products The M87C51FB is an enhanced version of the M87C51 Its added
features make it an even more powerful microcontroller for applications that require Pulse Width Modulation
High Speed I O and up down counting capabilities such as motor control It also has a more versatile serial
channel that facilitates multi-processor communications
November 1994
Order Number 271093-007
M87C51FB
271093 –1
Figure 1 M87C51FB Block Diagram
2
M87C51FB
TTL inputs Port 0 pins that have 1’s written to them
float and in that state can be used as high-imped-
ance inputs
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory In this application it uses strong inter-
nal pullups when emitting1’s and can source and
sink several LS TTL inputs
Port 0 also receives the code bytes during EPROM
programming and outputs the code bytes during
program verification External pullup resistors are re-
quired during program verification
Port 1 Port 1 is an 8-bit bidirectional I O port with
internal pullups The Port 1 output buffers can drive
LS TTL inputs Port 1 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 1
pins that are externally being pulled low will source
current (I
IL
on the data sheet) because of the inter-
nal pullups
271093 –2
DIP
In addition Port 1 serves the functions of the follow-
ing special features of the M87C51FB
Port Pin
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
P1 6
P1 7
Alternate Function
T2 (External Count Input to Timer
Counter 2)
T2EX (Timer Counter 2 Capture
Reload Trigger and Direction Control)
ECI (External Count Input to the PCA)
CEX0 (External I O for Compare
Capture Module 0)
CEX1 (External I O for Compare
Capture Module 1)
CEX2 (External I O for Compare
Capture Module 2)
CEX3 (External I O for Compare
Capture Module 3)
CEX4 (External I O for Compare
Capture Module 4)
LCC GULLWING J-LEAD
271093 – 20
Figure 2 M87C51FB Pin Connections
Port 1 receives the low-order address bytes during
EPROM programming and verifying
Port 2 Port 2 is an 8-bit bidirectional I O port with
internal pullups The Port 2 output buffers can drive
LS TTL inputs Port 2 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 2
pins that are externally being pulled low will source
current (I
IL
on the data sheet) because of the inter-
nal pullups
PIN DESCRIPTIONS
V
CC
Supply voltage
V
SS
Circuit ground
Port 0 Port 0 is an 8-bit open drain bidirectional I O
port As an output port each pin can sink several LS
3
M87C51FB
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX DPTR) In this application it
uses strong internal pullups when emitting 1’s Dur-
ing accesses to external Data Memory that use 8-bit
addresses (MOVX Ri) Port 2 emits the contents of
the P2 Special Function Register
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verifica-
tion
Port 3 Port 3 is an 8-bit bidirectional I O port with
internal pullups The Port 3 output buffers can drive
LS TTL inputs Port 3 pins that have 1’s written to
them are pulled high by the internal pullups and in
that state can be used as inputs As inputs Port 3
pins that are externally being pulled low will source
current (I
IL
on the data sheet) because of the pull-
ups
Port 3 also serves the functions of various special
features of the M8051 Family as listed below
Port Pin
P3 0
P3 1
P3 2
P3 3
P3 4
P3 5
P3 6
P3 7
Alternate Function
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
When the M87C51FB is executing code from exter-
nal Program Memory PSEN is activated twice each
machine cycle except that two PSEN activations
are skipped during each access to external Data
Memory
EA V
PP
External Access enable EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH Note however that if either of
the Program Lock bits are programmed EA will be
internally latched on reset
EA should be strapped to V
CC
for internal program
executions
This pin also receives the programming supply volt-
age (V
PP
) during EPROM programming
XTAL1 Input to the inverting oscillator amplifier
XTAL2 Output from the inverting oscillator amplifier
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output respec-
tively of an inverting amplifier which can be config-
ured for use as an on-chip oscillator as shown in
Figure 3 Either a quartz crystal or ceramic resonator
may be used More detailed information concerning
the use of the on-chip oscillator is available in Appli-
cation Note AP-155 ‘‘Oscillators for Microcontrol-
lers ’’
To drive the device from an external clock source
XTAL1 should be driven while XTAL2 floats as
shown in Figure 4 There are no requirements on the
duty cycle of the external clock signal since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop but minimum and maximum
high and low times specified on the data sheet must
be observed
RST Reset input A high on this pin for two machine
cycles while the oscillator is running resets the de-
vice An internal pulldown resistor permits a power-
on reset with only a capacitor connected to V
CC
ALE Address Latch Enable output pulse for latching
the low byte of the address during accesses to ex-
ternal memory This pin (ALE PROG) is also the
program pulse input during EPROM programming for
the M87C51FB
In normal operation ALE is emitted at a constant
rate of
the oscillator frequency and may be used
for external timing or clocking purposes Note how-
ever that one ALE pulse is skipped during each ac-
cess to external Data Memory
Throughout the remainder of this data sheet ALE
will refer to the signal coming out of the ALE PROG
pin and the pin will be referred to as the ALE PROG
pin
PSEN Program Store Enable is the read strobe to
external Program Memory
4
271093 –3
C1 C2
e
30 pF
g
10 pF for Crystals
e
10 pF for Ceramic Resonators
Figure 3 Oscillator Connections
M87C51FB
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that
puts the device into Power Down
DESIGN CONSIDERATION
271093 –4
Ambient light is known to affect the internal RAM
contents during operation If the M87C51FB ap-
plication requires the part to be run under ambi-
ent lighting an opaque label should be placed
over the window to exclude light
Figure 4 External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during Idle but
the processor stops executing instructions Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs The PCA timer counter can
optionally be left running or paused during Idle
Mode
When the Idle Mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
POWER DOWN MODE
To save even more power a Power Down Mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down Mode is terminated
On the M87C51FB either a hardware reset or an
external interrupt can cause an exit from Power
Down Reset redefines all the SFRs but does not
change the on-chip RAM An external interrupt al-
lows both the SFRs and on-chip RAM to retain their
values
To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before V
CC
is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the
M87C51FB without the M87C51FB having to be re-
moved from the circuit The ONCE Mode is invoked
by
1) Pull ALE low while the device is in reset and
PSEN is high
2) Hold ALE low as RST is deactivated
While the device is in ONCE Mode the Port 0 pins
go into a float state and the other port pins and ALE
and PSEN are weakly pulled high The oscillator cir-
cuit remains active While the M87C51FB is in this
mode an emulator or test CPU can be used to drive
the circuit Normal operation is restored when a nor-
mal reset is applied
Table 1 Status of the External Pins during Idle and Power Down
Mode
Idle
Idle
Power Down
Power Down
Program
Memory
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Data
Float
Data
Float
PORT1
Data
Data
Data
Data
PORT2
Data
Address
Data
Data
PORT3
Data
Data
Data
Data
NOTE
For more detailed information on the reduced power modes refer to Application Note AP-255 ‘‘Designing with the
M80C51BH’’
5
