FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-28500-5E
ASSP
AD/DA CONVERTER
MB40166/MB40176
1-CHANNEL 6-BIT AD/DA CONVERTER WITH CLAMP
CIRCUIT
The Fujitsu MB40166 and MB40176 are low power 6-bit AD/DA converter which
is fabricated with Fujitsu Advanced Bipolar Technology. MB40166 and MB40176
have the same basic circuits and functions, with the only difference being that
MB40166 has an independent analog input terminal for the A/D section and a
clamp voltage output terminal, while MB40176 has an analog input in the A/D
section internally connected with the clamp circuit.
Since both models contain a single-chip clamp circuit and a reference voltage
circuit, they are ideal for video signal processing.
•
•
•
•
•
•
•
•
•
Resolution
Linearity Error
Maximum Conversion Rate
Analog Input Voltage Range
0 to 1.0 V (MB40176)
Analog Output Voltage Range
Digital I/O Level
Power Supply Voltage
Power Dissipation:300 mW typ.
Package
28pin Plastic FLAT Package
28pin Plastic DIP Package
:6 bits
:±0.8% max.
:20 MSPS min.
:V
REF
to V
CCA
(MB40166)
:V
CC
to V
CC
-1 V
:TTL Level
:+5 V
PLASTIC PACKAGE
FPT-28P-M01
(Suffix : -PF)
(Suffix : -P)
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Power Supply Voltage
Digital Input Voltage
Analog Input Voltage
Storage Temperature
Symbol
V
CCA
, V
CCD
V
IND
V
INA
T
STG
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CCA
+0.5
-55 to +125
Unit
V
V
V
°C
PLASTIC PACKAGE
DIP-28P-M03
NOTE:
Permanent device damage may occur if the above
Absolute Maximum
Ratings
are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.
1
MB40166/MB40176
s
PIN ASSIGNMENT
(TOP VIEW)
DACK
(MSB)
(TOP VIEW)
28
27
26
25
24
23
D.GND
V
CCD
A.GND
V
CCA
V
OUT
COMP
V
REF
V
INA
V
CLMP
(N.C.)
V
CCA
A.GND
V
CCD
D.GND
(MSB)
(LSB)
(LSB)
(MSB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MB40166
DACK
D
D1
D
D2
D
D3
D
D4
D
D5
D
D6
D
A6
D
A5
D
A4
D
A3
D
A2
D
A1
ADCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MB40176
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D.GND
V
CCD
A.GND
V
CCA
V
OUT
COMP
V
REF
C
2
C
1
V
IN
V
CCA
A.GND
V
CCD
D.GND
D
D1
D
D2
D
D3
D
D4
D
D5
(LSB)
(LSB)
D
D6
D
A6
D
A5
D
A4
D
A3
D
A2
22
21
20
19
18
17
16
15
(MSB)
D
A1
ADCK
(FPT-28P-M01)
(DIP-28P-M03)
(FPT-28P-M01)
(DIP-28P-M03)
Note
: The functions of the terminals within the dotted lines above are different for MB40166 and MB40176.
2
MB40166/MB40176
s
BLOCK DIAGRAM
•
MB40166
0.8V
CCA
V
CLMP
20
CLAMP
REFERENCE
VOLTAGE
GENERATOR
V
INA
21
ADCK
14
V
CCA
0.8V
CCA
R
1
1
13
0.8V
CCA
(MSB)
D
A1
D
A2
R
2
63 to 6
ENCODER
LATCH
&
BUFFER
12
11
D
A3
R
62
10
D
A4
9
D
A5
D
A6
(LSB)
8
R
63
R
2
V
REF
22
DACK
D
D1
(MSB)
to
D
D6
(LSB)
1
2
6
6
7
MASTER
SLAVE
REGISTER
6
BUFFER
6
CURRENT
SWITCH
6
R-2R
RESISTOR
NETWORK
24
V
OUT
15
28
17
26
16
27
18
25
23
D.GND
A.GND
V
CCD
V
CCA
COMP
Note
: The circuits within the dotted lines above are different for MB40166 and MB40176.
3
MB40166/MB40176
s
BLOCK DIAGRAM (Continued)
•
MB40176
V
IN
C
1
C
2
19
20
21
0.8V
CCA
CLAMP
REFERENCE
VOLTAGE
GENERATOR
ADCK
14
V
CCA
0.8V
CCA
R
1
1
13
0.8V
CCA
(MSB)
D
A1
D
A2
R
2
63 to 6
ENCODER
LATCH
&
BUFFER
12
11
D
A3
R
62
10
D
A4
D
A5
9
8
R
D
A6
(LSB)
63
R
2
V
REF
22
DACK
D
D1
(MSB)
to
D
D6
(LSB)
1
2
6
6
7
MASTER
SLAVE
REGISTER
6
BUFFER
6
CURRENT
SWITCH
6
R-2R
RESISTOR
NETWORK
24
V
OUT
15
28
17
26
16
27
18
25
23
D.GND
A.GND
V
CCD
V
CCA
COMP
Note
: The circuits within the dotted lines above are different for MB40166 and MB40176.
4
MB40166/MB40176
s
PIN DESCRIPTIONS
Section
Pin No.
40166
21
–
22
A/D
8 to 13
20
–
–
14
24
2 to 7
D/A
23
1
18, 25
16, 27
17, 26
15, 28
Other
19
–
–
20
21
40176
–
19
Symbol
V
INA
V
IN
V
REF
D
A1
to D
A6
V
CLMP
C
1
C
2
ADCK
V
OUT
D
D1
to D
D6
COMP
DACK
V
CCA
V
CCD
A.GND
D.GND
(N.C.)
I/O
I
I
O
O
O
–
–
I
O
I
–
I
–
–
–
–
–
Analog signal input.
Reference voltage output.
Reference voltage divided by the resistors, with the
output
voltage set to 0.8 x V
CCA
(V).
Digital signal outputs. (D
A1
: MSB, D
A6
: LSB)
Clamp voltage output.
Clamp capacitor is connected between these pins.
A/D conversion clock input.
Analog signal output.
Digital signal input. (D
D1
: MSB, D
D6
: LSB)
Phase compensation capacitor is connected.
Insert a capacitor of 1
µF
or more between this pin and
A.GND.
D/A conversion clock input.
Power supply for analog circuit. (+5 V)
Power supply for digital circuit. (+5 V)
Ground for analog circuit. (0 V)
Ground for digital circuit. (0 V)
No connection.
Function
Common
5
