FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20871-3E
FLASH MEMORY
CMOS
8 M (1 M
×
8/512 K
×
16) BIT
MBM29SL800TD/BD
-10/12
s
DESCRIPTION
The MBM29SL800TD/BD are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512
Kwords of 16 bits each. The MBM29SL800TD/BD are offered in a 48-pin TSOP (I) , and 48-ball FBGA packages.
These devices are designed to be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.
(Continued)
s
PRODUCT LINE UP
Part No.
Ordering Part No.
V
CC
= +2.0
V
±
0.2
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
MBM29SL800TD/MBM29SL800BD
−10
100
100
35
−12
120
120
50
s
PACKAGE
48-pin Plastic TSOP (I)
Marking Side
48-pin Plastic TSOP (I)
48-pin Plastic FBGA
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
(BGA-48P-M02)
MBM29SL800TD
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(Continued)
The standard MBM29SL800TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE) ,
write enable (WE) , and output enable (OE) controls.
The MBM29SL800TD/BD are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29SL800TD/BD are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29SL800TD/BD are erased when shipped from the
factory.
The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29SL800TD/BD memories electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.
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FEATURES
•
Single 1.8 V read, program, and erase
Minimizes system level power requirements
•
Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
•
Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix : TN
−
Normal Bend Type, TR
−
Reversed Bend Type)
48-ball FBGA (Package suffix : PBT)
•
Minimum 100,000 program/erase cycles
•
High performance
100 ns maximum access time
•
Sector erase architecture
One 8 Kword, two 4 Kwords, one 16 Kword, and fifteen 32 Kwords sectors in word mode
One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and fifteen 64 Kbytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
•
Boot Code Sector Architecture
T
=
Top sector
B
=
Bottom sector
•
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
•
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
•
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode
•
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
•
Sector protection
Hardware method disables any combination of sectors from program or erase operations
•
Sector Protection set function by Extended sector Protect command
•
Temporary sector unprotection
Temporary sector unprotection via the RESET pin
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
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s
PIN ASSIGNMENTS
TSOP (I)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
N.C.
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
Standard Pinout
(FPT-48P-M19)
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
RY/BY
N.C.
N.C.
RESET
WE
N.C.
N.C.
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Reverse Pinout
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
(FPT-48P-M20)
(Continued)
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(Continued)
FBGA
(TOP VIEW)
Marking side
A6
A
13
A5
A
9
A4
B6
A
12
B5
A
8
B4
C6
A
14
C5
A
10
C4
D6
A
15
D5
A
11
D4
N.C.
D3
N.C.
D2
A
5
D1
A
1
E6
A
16
E5
DQ
7
E4
DQ
5
E3
DQ
2
E2
DQ
0
E1
A
0
F6
G6
H6
BYTEDQ
15
/A
-1
V
SS
F5
DQ
14
F4
DQ
12
F3
DQ
10
F2
DQ
8
F1
CE
G5
DQ
13
G4
V
CC
G3
DQ
11
G2
DQ
9
G1
OE
H5
DQ
6
H4
DQ
4
H3
DQ
3
H2
DQ
1
H1
V
SS
WE RESET N.C.
A3
RY/BY
A2
A
7
A1
A
3
B3
N.C.
B2
A
17
B1
A
4
C3
A
18
C2
A
6
C1
A
2
(BGA-48P-M02)
5
