Freescale Semiconductor
Document Number: MC44CC373
Rev 3.2, 04/2009
CMOS Audio/Video RF Modulators
The MC44CC373 / MC44CC374 CMOS family of RF modulators is the latest
generation of the legacy MC44BS373/4 family of devices.
The MC44CC373/MC44CC374 RF modulators are designed for use in VCRs,
set-top boxes, and similar devices.They support multiple standards, and can be
programmed to support PAL, SECAM, or NTSC formats.
The devices are programmed by a high-speed I
2
C Bus.
A programmable, internal PLL, with on-chip LC tank covers the full UHF range.
The modulators incorporate a programmable, on-chip, sound subcarrier oscil-
lator that covers all broadcast standards. No external tank circuit components
are required, reducing PCB complexity and the need for external adjustments.
The PLL obtains its reference from a low cost 4 MHz crystal oscillator.
The devices are available in a 16-pin SOIC, Pb-free package. These parts are
functionally equivalent to the MC44BS373/4 series, but are not direct drop-in re-
placements.
All devices now include the AUX
IN
found previously only on the 20-pin pack-
age option of the MC44BS373. This is a direct input for a modulated subcarrier
and is useful in BTSC or NICAM stereo sound or other subcarrier applications.
The MC44CC373CASEF has a secondary I
2
C address for applications using
two modulators on one I
2
C Bus.
MC44CC373CA
MC44CC373CAS
MC44CC374CA
MC44CC374T1A
CMOS AUDIO/VIDEO
RF MODULATORS
EF SUFFIX
SOIC-16 PACKAGE
CASE 751B-05
Features
•
•
•
•
•
•
•
Multi-TV standard support: NTSC, PAL, SECAM (B/G,
I, D/K, L, M/N).
UHF operation (460MHz to 880MHz)
Programmable UHF oscillator and sound subcarrier
oscillator.
On-chip tank circuits. No external varicaps inductors or
tuned components required.
Program control via 800 kHz high-speed I
2
C-bus.
Programmable Sound reference frequency (31.25 kHz
or 62.5 kHz)
Direct sound modulator input (FM and AM).
•
•
•
•
•
•
•
Auxiliary input bypasses AM/FM modulators for
NICAM or BTSC applications.
Video modulation depth (96% typ. in system L and
85% typ. in the other standards)
Programmable Peak White Clip levels
On-chip video test pattern generator with sound test
signal (1 kHz)
Low-power standby mode
Output inhibit during PLL Lock-up at power-ON
Logical output port controlled by I
2
C-bus
ORDERING INFORMATION
Orderable Part Number
(1)
Replaces Part
Number
MC44BS373CAD
Default
Frequency
(MHz)
591.25
591.25
591.25
871.25
871.25
RF
OUT(2)
(dBμV)
I
2
C
Write
Address
0xCA
0xCE
0xCA
0xCA
0xCA
PAL or
NTSC
Capability
Yes
Yes
Yes
Yes
Yes
SECAM
(system L)
Capability
Yes
Yes
No
No
No
AUX
IN
MC44CC373CAEF, R2
MC44CC373CASEF, R2
MC44CC374CAEF, R2
MC44BS373CAEF
MC44BS373CAFC
MC44BS373CAFC
MC44BS374CAD
MC44BS374CAEF
MC44BS374T1D
MC44BS374T1EF
MC44BS374T1AD
MC44BS374T1AEF
89
89
89
89
89
Yes
Yes
Yes
Yes
Yes
MC44CC374T1AEF, R2
1. All orderable parts are in a 16-pin SOIC, with temperature range of 0°C to +70°C ambient. For tape and reel, add the R2 suffix.
2. Refer to application note to obtain 82 dBμV or other RF levels.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
PIN DESCRIPTIONS
16-Pin SOIC Package
SDA
GND
LOP
XTAL
PREEM
AUDIO
IN
SPLFLT
VIDEO
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCL
AUX
IN
PLLFLT
No Connect
V
CC
RF
OUT
GND
V
CC
Figure 1. Pin Connections
Table 1. SO16 Package Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
SDA
GND
LOP
XTAL
PREEMP
AUDIO
IN
SPLFLT
VIDEO
IN
V
CC
GND
RF
OUT
V
CC
NC
PLLFLT
AUX
IN
SCL
I
2
C data
Ground
Description
Comments
Bidirectional serial data I/O port for setting configuration. Compatible with
0-5 V and 0-3.3 V I
2
C-bus.
Logical output port
controlled by I
2
C bus
Crystal
Pre-emphasis capacitor
Audio input
Sound PLL loop filter
Video input
Supply voltage
Ground
TV output signal
Supply voltage
No Connection
RF PLL loop filter
Auxiliary Input
I
2
C clock
Open collector output. Controlled by a single bit in the control register.
4 MHz crystal.
> 20 kΩ input impedance.
1 Volt peak-to-peak baseband video input
3.3 volt power input.
A 75
Ω
composite video output signal
3.3 Volt power input.
Do not make any connection to this pin.
Subcarrier input for stereo and NICAM applications
Serial control port data clock. Compatible with 0-5 V and 0-3.3 V I
2
C bus.
MC44CC373
2
Digital Home
Freescale Semiconductor
FUNCTIONAL OVERVIEW
Figure 2
shows a simplified block diagram of the
MC44CC373CA and MC44CC374CA modulators.
There are three main sections:
1.
2.
3.
A high speed I
2
C-compatible bus section for control and
programming.
A PLL section to synthesize the UHF output channel
frequency.
A modulator section, which accepts audio and video
inputs and modulates the RF carrier
An on-chip simple video test pattern generator with an au-
dio test signal is included, but is not shown in the block dia-
gram.
The MC44CC373/4CA operates as a multi-standard mod-
ulator and can handle the following systems using the same
external circuit components: B/G, I, D/K, L, M/N.
The different orderable part numbers provide: a choice in
the pre-programmed power-up default channel frequency,
the output power level and a pre-programmed secondary I
2
C
address.
VIDEO
IN
8
Peak
White Clip
Video
Modulator
L/BG
Internal Control Bus
SPLLFLT
7
V
CC
Clamp
12
MODULATOR
SECTION
Sound
Oscillator
and FM
Modulator
LPF
ALC
10
GND
6
Audio
Amplifier
5
31.25/62.5
kHz
Sound
PFD
L/BG
Program
Divider
AUDIO
IN
PREEM
V
CC
RF
OUT
11
9
LOP
3
RF Sound
Modulator
FM
L/BG
AM
AM Modulator
15
AUX
IN
VHF Dividers
BUS SECTION
SCL
SDA
16
1
High Speed
I
2
C Bus
Receiver
VCO and PLL SECTION
UHF OSC
(2 x F
o
)
Ref Divider
Phase
÷
128
Comp.
31.25 kHz
÷
2
Prescaler
÷
8
Program
Divider
÷
N11:N0
XO Prescaler
÷
1, 2 or 4
13
NO
CONNECT
XCO
2
14
4
GND
PLLFLT
XTAL
(4 MHz)
Figure 2. MC44CC373/374 Simplified Block Diagram
MC44CC373
Digital Home
Freescale Semiconductor
3
MODES OF OPERATION AND FUNCTIONAL DESCRIPTION
POWER ON SETTINGS
At power-on, the modulators are configured with pre-programmed default settings as listed in
Table 2.
Table 2. Power On Default Settings
Operating Mode
Part Number
UHF oscillator frequency (MHz)
RF
OUT
power (dBμV)
(1)
Sound frequency (MHz)
Sound reference frequency (kHz)
Logic Output Port (logic level)
Picture to sound ratio (dB)
Peak White Clip (state)
System Standards
Default Values
MC44CC373CA
591.25
89
5.5
31.25
Low
12
On
B/G
MC44CC373CAS
591.25
89
5.5
31.25
Low
12
On
B/G
MC44CC374CA
591.25
89
5.5
31.25
Low
12
On
B/G
MC44CC374T1A
871.25
89
5.5
31.25
Low
12
On
B/G
1. Refer to application note to obtain 82 dBμV or other RF levels.
POWER ON RESET
A power-on reset circuit holds the digital portion in reset
until the power supply has stabilized. Additionally a delay of
approximately 2 seconds allows the crystal oscillator to stabi-
lize before the digital section begins normal operation.
TRANSIENT OUTPUT INHIBIT
To minimize the risk of interference to other channels while
the UHF PLL is acquiring a lock on the desired frequency, the
Sound and Video modulators are turned OFF during a time
out period in two cases: Power On and UHF oscillator power
On (OSC bit switched from OFF to normal operation). There
is a time out of 262 ms until the output is enabled. This lets
the UHF PLL settle to its programmed frequency.
STANDBY MODES
During standby mode, the modulator is switched to low
power consumption. The sound oscillator, UHF oscillator, and
the video and sound modulator section’s bias are internally
turned OFF. The I
2
C bus section remains active.
The standby mode is set with a combination of 3 bits:
OSC=1, SO=1
and
ATT=1
for MC44CC373/374CAxxx
OSC=0, SO=1
and
ATT=1
for MC44CC374T1Axx
Programming of the Frequency Registers or the Optional
Control Registers is not allowed in Standby Mode.
SYSTEM L OR B/G SELECTION
The
SYSL
enable control bit internally switches the follow-
ing functions:
•
SYSL
= 0 enables B/G system
CRYSTAL REFERENCE OSCILLATOR
The reference crystal frequency is 4.0 MHz, the same as
for the legacy modulators.
The reference crystal oscillator if followed by a fixed di-
vide-by-128, resulting in a reference frequency of 31.25 kHz
for the phase detector.
UHF PLL SECTION
The UHF VCO runs at twice the desired RF frequency and
is divided by 2 before it is sent to the divide-by-8 prescaler
and then the programmable divider.
The programmable divider division-ratio is controlled by
the state of control bits
N0
to
N11
and is the binary number
for the number of 250 kHz steps in the desired RF
OUT
fre-
quency. The divider-ratio N for a desired frequency F (in
MHz) is given by:
(
2
×
F
)
128
-
-
N = -----------------
×
---------
16
4
with:
N = 2048
×
N11 + 1024
×
N10 +
……
+ 4
×
N2 + 2
×
N1 + N0
— Video modulation polarity: Negative
— Sound modulation: FM
•
SYSL
= 1 enables L system
NOTE:
Programming a division-ratio N = 0 is not allowed.
Programming of the N value must be performed while
the modulator is in normal mode, not standby mode.
— Video modulation polarity: Positive
— Sound modulation AM
MC44CC373
4
Digital Home
Freescale Semiconductor
UHF OSCILLATOR-VHF RANGE
For VHF range operation, the UHF oscillator can be inter-
nally divided by: 2, 4, 8, or 16. This is accomplished via the
special test mode bits,
X2:X0.
NOTE:
The MC44CC373/374 modulators are intended for
UHF operation. Using the digital dividers for VHF
operation will cause additional spurious content in the
RF
OUT
. Performance specifications for VHF operation
are not provided. The user must provide external
filtering on RF
OUT
to meet their VHF spurious
requirements.
SOUND SECTION
The sound oscillator is fully integrated and does not re-
quire any external components. An internal low-pass filter
and matched structure provide very low harmonics levels.
The sound modulator system consists of an FM modulator
incorporating the sound subcarrier oscillator. An AM modula-
tor is also included in the MC44CC373/374xxxx devices and
is enabled by the
SYSL
control bit for use in system L appli-
cations. The audio input signal is AC-coupled into the ampli-
fier, which then drives the modulators.
The sound reference divider is programmed by control bit
SRF,
resulting in a reference frequency of 31.25 kHz or
62.5 kHz. The sound subcarrier frequency is selected by con-
trol bits
SFD1:SFD0.
The subcarrier frequencies are 4.5, 5.5,
6.0 or 6.5 MHz. The power-up default value is 5.5 MHz.
A capacitor is connected to the external pin,
PREEM,
to
set the pre-emphasis time constant for the application. Infor-
mation on the selection of this filter may be found later in this
document under applications information.
LOGIC OUTPUT PORT (LOP)
The
LOP
pin controls any logic function. The primary ap-
plications for the
LOP
are to control an external attenuator or
an external switch, between the antenna input and TV output.
A typical attenuator application with PIN diode is shown in
Figure 3.
The
LOP
pin switches the PIN attenuator depend-
ing on the signal strength of the Antenna Input. This reduces
the risks of intermodulation in certain areas. The
LOP
can
also be used as an OFF position bypass switch or for other
logic functions in the application.
VIDEO SECTION - PEAK WHITE CLIP
The modulators require the following for proper video func-
tionality:
• A composite video input with negative going sync
pulses
• A nominal video level of < 1.14 V
This signal is AC-coupled to the video input where the
sync tip level is clamped.
The video signal is then passed to a Peak White Clip
(PWC) circuit. The PWC circuit function soft-clips the top of
the video waveform, if the sync tip amplitude to peak white
clip goes too high. This avoids carrier over-modulation by the
video.
The Peak White Clip level may be set via the Option Con-
trol Register 2, bits
PW1:PW0.
Clipping can be disabled by
software via bit
PWC
in the Control register.
TEST PATTERN GENERATOR
The modulators have a simple test pattern generator, that
may be enabled under I
2
C bus control, to permit a TV receiv-
er to easily tune to the modulator output. The pattern consists
of two white vertical bars on a black background and a 1 kHz
audio test signal.
The video test pattern consists of two signals generated by
the Digital section. One controls the sync pulse circuitry, and
the other controls the luminance circuitry. These signals are
logic levels that drive the video circuitry which creates a com-
posite signal with the proper levels for sync pulses and lumi-
nance as shown in
Figure 4.
TE2
7/10
3/10
TE1
0
4.75μs
10
20
24 28
30
40
44
50
60
64
TIME IN µS.
Vcc
Figure 4. Test Pattern Generator
Antenna
Input
TV Out
LOP pin
Figure 3. Typical Attenuator Application with Pin Diode
MC44CC373
Digital Home
Freescale Semiconductor
5
