MC74HC541A
Octal 3-State Noninverting
Buffer/Line Driver/Line
Receiver
High−Performance Silicon−Gate CMOS
The MC74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pull−up
resistors make them compatible with LSTTL outputs.
The HC541A is an octal noninverting buffer/line driver/line
receiver designed to be used with 3−state memory address drivers,
clock drivers, and other bus−oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active−low output enables.
The HC541A is similar in function to the HC540A, which has
inverting outputs.
Features
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MARKING
DIAGRAMS
20
20
MC74HC541AN
AWLYYWWG
1
20
20
1
SOIC−20
DW SUFFIX
CASE 751D
1
20
20
1
TSSOP−20
DT SUFFIX
CASE 948E
1
A
WL, L
YY, Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
HC
541A
ALYWG
G
HC541A
AWLYYWWG
1
PDIP−20
N SUFFIX
CASE 738
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 8
1
Publication Order Number:
MC74HC541A/D
MC74HC541A
V
CC
OE2
20
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
OE1
L
L
H
X
FUNCTION TABLE
Inputs
OE2
L
L
X
H
A
L
H
X
X
Output Y
L
H
Z
Z
1
OE1
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
GND
Figure 1. Pinout: 20−Lead Packages
(Top View)
2
3
4
5
6
7
8
9
1
19
18
17
16
15
14
13
12
11
PIN 20 = V
CC
PIN 10 = GND
X = Don’t Care
Z = High Impedance
A1
A2
A3
Data
Inputs
A4
A5
A6
A7
A8
Output
Enables
OE1
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Noninverting
Outputs
Figure 2. Logic Diagram
ORDERING INFORMATION
Device
MC74HC541ANG
MC74HC541ADWG
MC74HC541ADWR2G
NLV74HC541ADWR2G*
MC74HC541ADTG
MC74HC541ADTR2G
Package
PDIP−20
(Pb−Free)
SOIC−20 WIDE
(Pb−Free)
Shipping
†
18 Units / Rail
38 Units / Rail
1000 Tape & Reel
75 Units / Rail
2500 Tape & Reel
NLV74HC541ADTR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
TSSOP−20
(Pb−Free)
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2
MC74HC541A
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
DC Supply Voltage
DC Input Voltage
DC Output Voltage (Note 1)
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
PDIP
SOIC
TSSOP
PDIP
SOIC
TSSOP
Parameter
Value
*0.5
to
)7.0
*0.5 v
V
I
v
V
CC
)0.5
*0.5 v
V
O
v
V
CC
)0.5
$20
$35
$35
$75
$75
*65
to
)150
260
)150
67
96
128
750
500
450
Level 1
Oxygen Index: 30%
−
35%
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 85_C (Note 5)
UL 94 V−0 @ 0.125 in
> 4000
> 300
> 1000
$300
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
P
D
Power Dissipation in Still Air at 85_C
mW
MSL
F
R
V
ESD
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
I
Latchup
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
ÎÎÎ
Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î
ÎÎÎ Î
Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎ Î
Î
Î
Î
Î
ÎÎÎÎÎÎ
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
V
CC
DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
2.0
0
6.0
V
V
V
IN
,
V
OUT
T
A
DC Input Voltage, Output Voltage
V
CC
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Figure 3)
*55
0
0
0
)125
1000
500
400
_C
ns
t
r
, t
f
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
Symbol
Parameter
Min
Max
Unit
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3
MC74HC541A
DC CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Condition
V
OUT
= 0.1 V
|I
OUT
|
≤
20
mA
V
OUT
= V
CC
−
0.1 V
|I
OUT
|
≤
20
mA
V
IN
= V
IL
|I
OUT
|
≤
20
mA
V
IN
= V
IL
|I
OUT
|
≤
3.6 mA
|I
OUT
|
≤
6.0 mA
|I
OUT
|
≤
7.8 mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
OUT
|
≤
3.6 mA
|I
OUT
|
≤
6.0 mA
|I
OUT
|
≤
7.8 mA
3.0
4.5
6.0
6.0
6.0
*55
to
25_C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
$0.1
$0.5
v85_C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
$1.0
$5.0
v125_C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
$1.0
$10.0
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
V
OH
Minimum High−Level Output Voltage
V
V
OL
Maximum Low−Level Output Voltage
V
IN
= V
IH
|I
OUT
|
≤
20
mA
V
IN
= V
IH
I
IN
I
OZ
Maximum Input Leakage Current
Maximum 3−State Leakage Current
V
IN
= V
CC
or GND
Output in High Impedance State
V
IN
= V
IL
or V
IH
V
OUT
= V
CC
or GND
V
IN
= V
CC
or GND
I
OUT
= 0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
6.0
4
40
160
mA
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZL
,
t
PZH
t
TLH
,
t
THL
C
IN
C
OUT
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 5)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
*55
to
25_C
80
30
18
15
110
45
25
21
110
45
25
21
60
22
12
10
10
15
v85_C
100
40
23
20
140
60
31
26
140
60
31
26
75
28
15
13
10
15
v125_C
120
55
28
25
165
75
38
31
165
75
38
31
90
34
18
15
10
15
Unit
ns
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
ns
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
ns
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
ns
Maximum Input Capacitance
Maximum 3−State Output Capacitance (High Impedance State Output)
pF
pF
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
Power Dissipation Capacitance (Per Buffer) (Note 7)
35
pF
7. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
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4
MC74HC541A
t
r
90%
INPUT A
t
PLH
50%
10%
t
TLH
t
THL
90%
50%
10%
t
PHL
GND
t
f
V
CC
OUTPUT Y
Figure 3. Switching Waveform
V
CC
OE1 or OE2
t
PZL
OUTPUT Y
t
PZH
OUTPUT Y
50%
HIGH
IMPEDANCE
50%
50%
t
PLZ
50%
GND
HIGH
IMPEDANCE
10%
t
PHZ
90%
V
OH
V
OL
Figure 4. Switching Waveform
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
and t
PZH
.
C
L
*
*Includes all probe and jig capacitance
Figure 6. Test Circuit
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