MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM63R836/D
8M Late Write HSTL
The MCM63R836/918 is an 8M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM63R918
(organized as 512K words by 18 bits) and the MCM63R836 (organized as 256K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
CMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK; all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control
signals. Read data is also driven on the rising edge of CK.
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)
and output voltage (VDDQ ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
•
•
•
•
•
•
•
•
•
•
Byte Write Control
2.5 V – 5% to 3.3 V + 10% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM63R836/918–3.0 = 3.0 ns
MCM63R836/918–3.3 = 3.3 ns
MCM63R836/918–3.7 = 3.7 ns
MCM63R836/918–4.0 = 4.0 ns
MCM63R836/918–4.4 = 4.4 ns
•
Sleep Mode Operation (ZZ pin)
•
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip Plastic
Ball Grid Array (PBGA) or Flipped Chip Ceramic Ball Grid Array (CBGA)
Packages
MCM63R836
MCM63R918
FC PACKAGE
PBGA
CASE 999D–01
RS PACKAGE
CBGA
CASE 999B–01
5/3/99
©
Motorola, Inc. 1999
MOTOROLA FAST SRAM
MCM63R836•MCM63R918
1
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
REGISTERS
DATA IN
REGISTER
DQ
DATA OUT
REGISTER
SA
MEMORY
ARRAY
SW
SBx
SW
REGISTERS
CONTROL
LOGIC
CK
G
SS
REGISTERS
SS
PIN ASSIGNMENTS
TOP VIEW
MCM63R836
1
A
B
C
D
E
DQc
F
G
DQc
H
J
K
L
DQd
M
VDDQ DQd
N
P
R
T
U
DQd
DQd
NC
NC
DQd
DQd
SA
NC
VSS
VSS
VSS
VSS
SA
TDI
SW
SA
SA
VDD
SA
TCK
VSS
VSS
VSS
VDD
SA
TDO
DQa VDDQ
DQa
DQa
SA
NC
DQa
DQa
NC
ZZ
N
P
R
T
NC
U
SA
SA
TDI
NC
TCK
SA
TDO
SA
ZZ
VDDQ TMS
NC VDDQ
DQd
SBd
CK
SBa
DQa
DQa
M
VDDQ DQb
DQb
NC
NC
NC
DQb
SA
VSS
VSS
VSS
VSS
SW
SA
SA
VDD
VSS
VSS
VSS
VDD
NC VDDQ
DQa
NC
SA
NC
DQa
NC
DQc
DQc
DQc
SBc
VSS
Vref
VSS
NC
NC
VDD
CK
SBb
VSS
Vref
VSS
DQb
DQb
DQb
DQb
H
J
K
L
DQc
VSS
VSS
SS
G
VSS
VSS
DQb
DQb
F
G
NC
DQb
DQb
NC
SBb
VSS
Vref
VSS
VSS
NC
NC
VDD
CK
CK
VSS
VSS
Vref
VSS
SBa
NC
DQa
DQa
NC
VDDQ DQc
DQb VDDQ
VDDQ
NC
NC
DQc
2
SA
NC
SA
DQc
3
SA
SA
SA
VSS
4
NC
NC
VDD
ZQ
5
SA
SA
SA
VSS
6
SA
SA
SA
DQb
7
VDDQ
NC
NC
DQb
A
B
C
D
E
NC
VDDQ
DQb
NC
VSS
VSS
SS
G
VSS
VSS
NC
DQa
DQa VDDQ
1
VDDQ
NC
NC
DQb
2
SA
NC
SA
NC
MCM63R918
3
SA
SA
SA
VSS
4
NC
NC
VDD
ZQ
5
SA
SA
SA
VSS
6
SA
SA
SA
DQa
7
VDDQ
NC
NC
NC
VDDQ VDD
DQd
DQd
VDD VDDQ
DQa
DQa
VDDQ VDD
NC
DQb
DQb
NC
VDD VDDQ
NC
DQa
DQa
NC
VDDQ TMS
NC VDDQ
MCM63R836•MCM63R918
2
MOTOROLA FAST SRAM
MCM63R836 PIN DESCRIPTIONS
Pin Locations
4K
4L
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
4F
2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C,
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T
5L, 5G, 3G, 3L
(a), (b), (c), (d)
4E
4M
4U
3U
5U
2U
4D
7T
4C, 2J, 4J, 6J, 4R, 5R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3J, 5J
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R
4A, 1B, 2B, 4B, 7B, 1C, 7C,
4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U
Symbol
CK
CK
DQx
Type
Input
Input
I/O
Description
Address, data in, and control input register clock. Active high.
Address, data in, and control input register clock. Active low.
Synchronous Data I/O.
G
SA
SBx
Input
Input
Input
Output Enable functionality not supported. Must be tied to VSS or
driven to
≤
VIL Max.
Synchronous Address Inputs: Registered on the rising clock edge.
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
Synchronous Chip Enable: Registered on the rising clock edge,
active low.
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
Test Clock (JTAG).
Test Data In (JTAG).
Test Data Out (JTAG).
Test Mode Select (JTAG).
Programmable Output Impedance: Programming pin.
Enables sleep mode, active high.
Core Power Supply.
Output Power Supply: Provides operating power for output buffers.
Input Reference: Provides reference voltage for input buffers.
Ground.
No Connection: There is no connection to the chip.
SS
SW
TCK
TDI
TDO
TMS
ZQ
ZZ
VDD
VDDQ
Vref
VSS
NC
Input
Input
Input
Input
Output
Input
Input
Input
Supply
Supply
Supply
Supply
—
MOTOROLA FAST SRAM
MCM63R836•MCM63R918
3
MCM63R918 PIN DESCRIPTIONS
Pin Locations
4K
4L
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
4F
2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C,
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
5L, 3G
(a), (b)
4E
4M
4U
3U
5U
2U
4D
7T
4C, 2J, 4J, 6J, 4R, 5R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3J, 5J
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R
4A, 1B, 2B, 4B, 7B, 1C, 7C,
2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U
Symbol
CK
CK
DQx
G
SA
SBx
Type
Input
Input
I/O
Input
Input
Input
Description
Address, data in, and control input register clock. Active high.
Address, data in, and control input register clock. Active low.
Synchronous Data I/O.
Output Enable functionality not supported. Must be tied to VSS or
driven to
≤
VIL Max.
Synchronous Address Inputs: Registered on the rising clock edge.
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
Synchronous Chip Enable: Registered on the rising clock edge,
active low.
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
Test Clock (JTAG).
Test Data In (JTAG).
Test Data Out (JTAG).
Test Mode Select (JTAG).
Programmable Output Impedance: Programming pin.
Enables sleep mode, active high.
Core Power Supply.
Output Power Supply: Provides operating power for output buffers.
Input Reference: Provides reference voltage for input buffers.
Ground.
No Connection: There is no connection to the chip.
SS
SW
TCK
TDI
TDO
TMS
ZQ
ZZ
VDD
VDDQ
Vref
VSS
NC
Input
Input
Input
Input
Output
Input
Input
Input
Supply
Supply
Supply
Supply
—
MCM63R836•MCM63R918
4
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS, See Note)
Rating
Core Supply Voltage
Output Supply Voltage
Voltage On Any Pin Other Than JTAG
Voltage On Any JTAG Pin
Input Current (per I/O)
Output Current (per I/O)
Operating Temperature
Temperature Under Bias
Storage Temperature
Symbol
VDD
VDDQ
Vin
VJTAG
Iin
Iout
TA
Tbias
Tstg
Value
– 0.5 to + 3.9
– 0.5 to + 2.5
– 0.5 to + 2.5
– 0.5 to + 3.9
±
50
±
25
0 to + 70
–10 to + 85
– 55 to + 125
Unit
V
V
V
V
mA
mA
°C
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high–impedance circuit.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Junction to Ambient (Still Air)
Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)
Junction to Board (Bottom)
Junction to Case (Top)
Single–Layer Board
Four–Layer Board
Symbol
R
θJA
R
θJA
R
θJA
R
θJB
R
θJC
Max
50
39
27
23
1
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
1, 2
1, 2
3
4
5
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Measured using a four–layer test board with two internal planes.
4. Indicates the average thermal resistance between the die and the printed circuit board as measured by the ring cold plate method.
5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CLOCK TRUTH TABLE
K
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
X
ZZ
L
L
L
L
L
L
L
L
L
H
SS
L
L
L
L
L
L
L
H
H
X
SW
H
L
L
L
L
L
L
H
L
X
SBa
X
L
H
H
H
L
H
X
X
X
SBb
X
H
L
H
H
L
H
X
X
X
SBc
X
H
H
L
H
L
H
X
X
X
SBd
X
H
H
H
L
L
H
X
X
X
DQ (n)
X
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
X
High–Z
High–Z
DQ (n + 1)
Dout 0 – 35
Din 0 – 8
Din 9 – 17
Din 18 – 26
Din 27 – 35
Din 0 – 35
High–Z
High–Z
High–Z
High–Z
Mode
Read Cycle All Bytes
Write Cycle 1st Byte
Write Cycle 2nd Byte
Write Cycle 3rd Byte
Write Cycle 4th Byte
Write Cycle All Bytes
Abort Write Cycle
Deselect Cycle
Deselect Cycle
Sleep Mode
MOTOROLA FAST SRAM
MCM63R836•MCM63R918
5
