MM74C74 Dual D-Type Flip-Flop
October 1987
Revised May 2002
MM74C74
Dual D-Type Flip-Flop
General Description
The MM74C74 dual D-type flip-flop is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement transistors. Each flip-flop
has independent data, preset, clear and clock inputs and Q
and Q outputs. The logic level present at the data input is
transferred to the output during the positive going transition
of the clock pulse. Preset or clear is independent of the
clock and accomplished by a low level at the preset or clear
input.
Features
s
Supply voltage range:
3V to 15V
Drive 2 LPT
2
L loads
s
Tenth power TTL compatible:
s
Low power:
50 nW (typ.)
s
High noise immunity: 0.45 V
CC
(typ.)
s
Medium speed operation: 10 MHz (typ.) with 10V
supply
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm system
• Industrial electronics
• Remote metering
• Computers
Ordering Code:
Order Number
MM74C74M
MM74C74N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Preset
0
0
1
1
Clear
0
1
0
1
Q
n
0
1
0
Q
n
(Note 1)
Q
n
0
0
1
Q
n
(Note 1)
Note 1:
No change in output from previous state.
Note: A logic “0” on clear sets Q to logic “0”.
A logic “0” on preset sets Q to logic “1”.
Top View
© 2002 Fairchild Semiconductor Corporation
DS005885
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MM74C74
Logic Diagram
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2
MM74C74
Absolute Maximum Ratings
(Note 2)
Voltage at Any Pin (Note 2)
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Dual-In-Line
Small Outline
Lead Temperature
(Soldering, 10 seconds)
Operating V
CC
Range
V
CC
(Max)
260
°
C
3V to 15V
18V
700 mW
500 mW
Note 2:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
−
0.3V to V
CC
+
0.3V
−
55
°
C to
+
125
°
C
−
65
°
C to
+
150
°
C
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
Logical “1” Input Current
Logical “0” Input Current
Supply Current
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
15V
V
CC
=
15V
V
CC
=
15V
V
CC
=
4.75V
V
CC
=
4.75V
V
CC
=
4.75V, I
D
= −360 µA
V
CC
=
4.75V, I
D
=
360
µA
V
CC
=
5V, V
IN(0)
=
0V
T
A
=
25°C, V
OUT
=
0V
V
CC
=
10V, V
IN(0)
=
0V
T
A
=
25°C, V
OUT
=
0V
V
CC
=
5V, V
IN(1)
=
5V
T
A
=
25°C, V
OUT
=
V
CC
V
CC
=
10V, V
IN(1)
=
10V
T
A
=
25°C, V
OUT
=
V
CC
2.4
0.4
V
CC
−
1.5
0.8
V
V
V
−1.0
0.05
60
4.5
9.0
0.5
1.0
1.0
3.5
80
1.5
2.0
V
V
V
V
µA
µA
µA
Min
Typ
Max
Units
CMOS/LPTTL INTERFACE
OUTPUT DRIVE (See Family Characteristics Data Sheet)
−1.75
−8.0
1.75
8.0
mA
mA
mA
mA
3
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MM74C74
AC Electrical Characteristics
T
A
=
25
°
C, C
L
=
50 pF, unless otherwise noted
Symbol
C
IN
t
pd
Parameter
Input Capacitance
Propagation Delay Time to a
Logical “0” t
pd0
or Logical “1”
t
pd1
from Clock to Q or Q
t
pd
t
pd
t
S0
, t
S1
t
H0
, t
H1
t
PW1
t
PW2
t
r
, t
f
f
MAX
C
PD
Propagation Delay Time to a
Logical “0” from Preset or Clear
Propagation Delay Time to a
Logical “1” from Preset or Clear
Time Prior to Clock Pulse that
Data Must be Present t
SETUP
Time after Clock Pulse that
Data Must be Held
Minimum Clock Pulse
Width (t
WL
=
t
WH
)
Minimum Preset and
Clear Pulse Width
Maximum Clock Rise
and Fall Time
Maximum Clock Frequency
Power Dissipation Capacitance
(Note 3)
Conditions
Any Input (Note 4)
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
V
CC
=
5V
V
CC
=
10V
(Note 5)
15.0
5.0
2.0
5.0
3.5
8.0
40
100
40
Min
Typ
5.0
180
70
180
70
250
100
50
20
−20
−8.0
100
40
100
40
0
0
250
100
160
70
300
110
300
110
400
150
Max
Units
pF
ns
ns
ns
ns
ns
ns
ns
µs
MHz
pF
Note 3:
AC Parameters are guaranteed by DC correlated testing.
Note 4:
Capacitance is guaranteed by periodic testing.
Note 5:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note—
AN-90.
Typical Applications
Ripple Counter (Divide by 2
n
)
74C Compatibility
Shift Register
Guaranteed Noise Margin as a Function of V
CC
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4
MM74C74
Switching Time Waveform
CMOS to CMOS
t
r
=
t
f
=
20 ns
AC Test Circuit
5
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