MM74HC251 8-Channel 3-STATE Multiplexer
September 1983
Revised February 1999
MM74HC251
8-Channel 3-STATE Multiplexer
General Description
The MM74HC251 8-channel digital multiplexer with 3-
STATE outputs utilizes advanced silicon-gate CMOS tech-
nology. Along with the high noise immunity and low power
consumption of standard CMOS integrated circuits, it pos-
sesses the ability to drive 10 LS-TTL loads. The large out-
put drive capability and 3-STATE feature make this part
ideally suited for interfacing with bus lines in a bus oriented
system.
This multiplexer features both true (Y) and complement
(W) outputs as well as a STROBE input. The STROBE
must be at a low logic level to enable this device. When the
STROBE input is HIGH, both outputs are in the high
impedance state. When enabled, address information on
the data select inputs determines which data input is routed
to the Y and W outputs. The 74HC logic family is speed,
function, as well as pinout compatible with the standard
74LS logic family. All inputs are protected from damage
due to static discharge by internal diode clamps to V
CC
and
ground.
Features
s
Typical propagation delay
Data select to Y: 26 ns
s
Wide supply range: 2–6V
s
Low power supply quiescent current:
80
µA
maximum (74HC)
s
3-STATE outputs for interface to bus oriented
systems
Ordering Code:
Order Number
MM74HC251M
MM74HC251SJ
MM74HC251MTC
MM74HC251N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
© 1999 Fairchild Semiconductor Corporation
DS005328.prf
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MM74HC251
Truth Table
Inputs
Select
C
X
L
L
L
L
H
H
H
H
H
=
HIGH Logic Level, L
=
LOW Logic Level
X
=
Irrelevant, Z
=
High Impedance (off)
D0, D1. . . D7
=
The level of the respective D input
Outputs
Strobe
S
H
L
L
L
L
L
L
L
L
Y
Z
D0
D1
D2
D3
D4
D5
D6
D7
W
Z
D0
D1
D2
D3
D4
D5
D6
D7
B
X
L
L
H
H
L
L
H
H
A
X
L
H
L
H
L
H
L
H
Logic Diagram
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2
MM74HC251
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260°C
600 mW
500 mW
−0.5
to
+7.0V
−1.5
to V
CC
+1.5V
−0.5
to V
CC
+0.5V
±20
mA
±25
mA
±50
mA
−65°C
to
+150°C
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
0
−40
V
CC
+85
V
°C
2
Max
6
Units
V
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
Conditions
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
8.0
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
±5
80
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
±10
160
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
I
IN
I
OZ
I
CC
Maximum Input
Current
Maximum 3-STATE
Leakage Current
Maximum Quiescent
Supply Current
Strobe
=
V
CC
V
OUT
=
V
CC
or GND
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
6.0V
6.0V
V
IN
=
V
CC
or GND
4.5V
6.0V
6.0V
4.5V
6.0V
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC251
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25
°
C, C
L
=
15 pF, t
r
=
t
f
=
6 ns
Symbol
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
PHZ
, t
PLZ
Parameter
Maximum Propagation Delay
A, B or C to Y
Maximum Propagation
Delay, A, B or C to W
Maximum Propagation
Delay, Any D to Y
Maximum Propagation
Delay, Any D to W
Maximum Output Enable
Time, W Output
Maximum Output Enable
Time, Y Output
Maximum Output Disable Time
W Output
Maximum Output Disable Time
Y Output
R
L
=
1 kΩ
C
L
=
50 pF
R
L
=
1 kΩ
C
L
=
50 pF
R
L
=
1 kΩ
C
L
=
5 pF
R
L
=
1 kΩ
C
L
=
5 pF
27
35
ns
26
40
ns
19
26
ns
19
27
ns
24
32
ns
22
29
ns
27
35
ns
Conditions
Typ
26
Guaranteed
Limit
35
Units
ns
AC Electrical Characteristics
C
L
=
50 pF, t
r
=
t
f
=
6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
V
CC
2.0V
4.5V
6.0V
t
PHL
, t
PLH
Maximum Propagation
Delay, A, B or C to W
t
PHL
, t
PLH
Maximum Propagation
Delay, any D to Y
t
PHL
, t
PLH
Maximum Propagation
Delay, any D to W
t
PZH
, t
PZL
Maximum Output Enable Time
W Output
t
PZH
, t
PZL
Maximum Output Enable Time
Y Output
t
PHZ
, t
PLZ
Maximum Output Disable Time
W Output
t
PHZ
, t
PLZ
Maximum Output Disable Time
Y Output
t
THL
, t
TLH
Maximum Output Rise
and Fall Time
C
PD
C
IN
Power Dissipation Capacitance (Note 5) (per package)
Maximum Input Capacitance
2
T
A
=
25°C
Typ
90
31
26
95
32
27
70
27
23
75
29
25
45
21
18
45
21
18
60
29
25
60
30
26
30
8
7
110
5
10
205
41
35
205
41
35
195
39
33
185
37
32
150
30
26
145
29
25
220
44
37
195
39
33
75
15
13
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
256
51
44
256
51
44
244
49
41
231
46
40
188
38
33
181
36
31
275
55
46
244
49
41
95
19
16
10
300
60
51
300
60
51
283
57
48
268
54
46
218
44
38
210
42
36
319
64
54
283
57
48
110
22
19
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
t
PHL
, t
PLH
Maximum Propagation Delay
A, B or C to Y
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
R
L
=
1 kΩ
2.0V
4.5V
6.0V
R
L
=
1 kΩ
2.0V
4.5V
6.0V
R
L
=
1 kΩ
2.0V
4.5V
6.0V
R
L
=
1 kΩ
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
V
CC
f
+
I
CC
.
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4
MM74HC251
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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