MM74HC86 — Quad 2-Input Exclusive OR Gate
May 2012
MM74HC86
Quad 2-Input Exclusive OR Gate
Features
Typical Propagation Delay: 9ns
Wide Operating Voltage Range: 2–6V
Low Input Current: 1mA Maximum
Low Quiescent Current: 20mA Max. (74 Series)
Output Drive Capability: 10 LS-TTL Loads
Description
The MM74HC86 exclusive OR gate utilizes advanced
silicon-gate CMOS technology to achieve operating
speeds similar to equivalent LS-TTL gates, while
maintaining the low power consumption and high noise
immunity characteristic of standard CMOS integrated
circuits. These gates are fully buffered and have a
fanout of 10 LS-TTL loads. The 74HC logic family is
functionally as well as pin-out compatible with the
standard 74LS logic family. All inputs are protected from
damage due to static discharge by internal diode clamps
to V
CC
and ground.
Table 1.
Truth Table
Inputs
Outputs
B
L
H
L
H
A
L
L
H
H
Note:
1.
Figure 1.
Pin Assignments (Top View)
Y
(1)
L
H
H
L
Y
½
A
B
½
A B
AB
Ordering Information
Part Number
MM74HC86M
MM74HC86MX
MM74HC86MTC
MM74HC86MTCX
Note:
2. Pb-Free package per JEDEC J-STD-020B.
-40 to +85°C
Operating
Temperature Range
Package
14-Lead, Small Outline Integrated Circuit
(SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead, Thin Shrink Small Outline Package
(TSSOP), JEDEC MO-153, 4.4mm Wide
Packing Method
Tube
Tape & Reel
Tube
Tape & Reel
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
MM74HC86 — Quad 2-Input Exclusive OR Gate
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
Absolute maximum ratings are stress ratings only. Unless otherwise specified, all voltages are referenced to ground.
Symbol
V
CC
V
IN
V
OUT
I
IK
, I
OK
I
OUT
I
CC
T
STG
T
L
P
D
Supply Voltage
DC Input Voltage
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
Parameter
Min.
-0.5
-1.5
-0.5
Max.
7.0
V
CC
+1.5
V
CC
+0.5
±20
±25
±50
Unit
V
V
V
mA
mA
mA
DC VCC or GND Current, per Pin
Storage Temperature Range
Lead Temperature (Soldering, 10 Seconds)
Power Dissipation
(3, 4)
-65
+150
260
600
°C
°C
mW
Note:
3. Power dissipation temperature derating — plastic “N” package: -12 mW/°C from 65°C to 85°C.
4. S.O. package only 500mW.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CC
V
IN
, V
OUT
T
A
t
R
, t
F
Supply Voltage
Parameter
DC Input or Output Voltage
Operating Temperature Range
Conditions
Min.
2
0
-40
Max.
6
V
CC
+85
1000
500
400
Unit
V
V
°C
ns
V
CC
= 2.0V
Input Rise or Fall Times
V
CC
= 4.5V
V
CC
= 6.0V
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
2
MM74HC86 — Quad 2-Input Exclusive OR Gate
DC Electrical Characteristics
(5)
Symbol
Parameter
Condition
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
V
IN
= V
IH
or V
IL
,
|I
OUT
|
≤
20µA
V
OH
Minimum HIGH Level
Output Voltage
V
IN
= V
IH
or V
IL
,
|I
OUT
|
≤
4.0mA
V
IN
= V
IH
or V
IL
,
|I
OUT
|
≤
5.2mA
V
IN
= V
IH
or V
IL
,
|I
OUT
|
≤
20µA
V
OL
Maximum LOW Level
Output Voltage
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
V
IN
= V
IH
or V
IL
,
|I
OUT
|
≤
4.0mA
V
IN
= V
IH
or V
IL
,
|I
OUT
|
≤
5.2mA
I
IN
I
CC
Maximum Input Current
Maximum Quiescent
Supply Current
V
IN
= V
CC
or GND
V
IN
= V
CC
or GND,
I
OUT
= 0mA
4.5
6.0
6.0
6.0
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=25°C
T
A
=-40 to T
A
=-55 to
+85°C
+125°C
Units
Typ.
V
IH
Minimum HIGH Level
Input Voltage
Guaranteed Limit
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
2.0
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
20
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.70
5.20
0.1
0.1
0.1
0.40
0.40
±1.0
40
mA
mA
V
V
V
V
V
IL
Maximum LOW Level
Input Voltage
Note:
5. For a power supply of 5V ±10%, the worst-case output voltages (V
OH
and V
OL
) occur for HC at 4.5V. Thus, the
4.5V values should be used when designing with this supply. Worst-case V
IH
and V
IL
occur at V
CC
= 5.5V and
4.5V, respectively. (The V
IH
values at 5V and 5.5V are 3.5V and 3.85V, respectively.) The worst-case leakage
current (I
IN
, I
CC
, and I
OZ
) occurs for CMOS at the higher voltage, so the 6.0V values should be used.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
3
MM74HC86 — Quad 2-Input Exclusive OR Gate
AC Electrical Characteristics
Symbol
Parameter
Conditions
C
L
= 15pF,
t
R
= t
F
= 6ns
V
CC
T
A
=25°C
T
A
=-40 to T
A
=-55 to
+85°C
+125°C
Unit
Typ.
t
PHL
, t
PLH
Maximum Propagation Delay
5.0
2.0
t
PHL
, t
PLH
Maximum Propagation Delay
4.5
6.0
2.0
4.5
6.0
C
PD
C
IN
Power Dissipation
Capacitance (per Gate)
(6)
Maximum Input Capacitance
12
60
12
10
30
8
7
25
5
Guaranteed Limit
20
120
24
20
75
15
13
151
30
26
95
19
16
179
36
30
110
22
19
s
ns
ns
t
TLH
, t
THL
Maximum Output Rise and
Fall Time
C
L
= 50pF,
t
R
= t
F
= 6ns
ns
pF
10
10
10
pF
Note:
2
6. C
PD
determines the no-load dynamic power consumption, P
D
= C
PD
V
CC
f + I
CC
V
CC
, and the no load dynamic
current consumption, I
S
= C
PD
V
CC
f + I
CC
.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
4
MM74HC86 — Quad 2-Input Exclusive OR Gate
Physical Dimensions
8.75
8.50
7.62
14
8
B
A
0.65
5.60
6.00
4.00
3.80
PIN ONE
INDICATOR
1
7
1.70
1.27
1.27
(0.33)
0.51
0.35
0.25
M
LAND PATTERN RECOMMENDATION
C B A
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.10
C
0.10 C
NOTES: UNLESS OTHERWISE SPECIFIED
0.25
0.19
R0.10
R0.10
8°
0°
0.50
0.25
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
X 45°
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
GAGE PLANE
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
0.36
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
0.90
0.50
(1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 2.
14-Lead, Small-Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 1983 Fairchild Semiconductor Corporation
MM74HC86 • Rev. 1.4.0
www.fairchildsemi.com
5
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