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MM74HCT373MTCX

Networking Modules XPort XE Ext. Temp. without Encryption

器件类别:逻辑    逻辑   

厂商名称:Fairchild

厂商官网:http://www.fairchildsemi.com/

器件标准:

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器件参数
参数名称
属性值
Brand Name
Fairchild Semiconductor
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Fairchild
零件包装代码
TSSOP
包装说明
TSSOP, TSSOP20,.25
针数
20
制造商包装代码
20LD, TSSOP, JEDEC MO-153, 4.4MM WIDE
Reach Compliance Code
compliant
ECCN代码
EAR99
系列
HCT
JESD-30 代码
R-PDSO-G20
JESD-609代码
e4
长度
6.5 mm
负载电容(CL)
50 pF
逻辑集成电路类型
BUS DRIVER
最大I(ol)
0.006 A
湿度敏感等级
1
位数
8
功能数量
1
端口数量
2
端子数量
20
最高工作温度
85 °C
最低工作温度
-40 °C
输出特性
3-STATE
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装等效代码
TSSOP20,.25
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法
TAPE AND REEL
峰值回流温度(摄氏度)
260
电源
5 V
Prop。Delay @ Nom-Sup
37 ns
传播延迟(tpd)
56 ns
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式
GULL WING
端子节距
0.65 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
4.4 mm
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www.onsemi.com
Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
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(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at
www.onsemi.com.
Please
email any questions regarding the system integration to
Fairchild_questions@onsemi.com.
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MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
February 1984
Revised May 2005
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The
MM74HCT373
octal
D-type
latches
and
MM74HCT374 Octal D-type flip flops advanced silicon-gate
CMOS technology, which provides the inherent benefits of
low power consumption and wide power supply range, but
are LS-TTL input and output characteristic & pin-out com-
patible. The 3-STATE outputs are capable of driving 15 LS-
TTL loads. All inputs are protected from damage due to
static discharge by internal diodes to V
CC
and ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to the OUTPUT CON-
TROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on positive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
s
TTL input characteristic compatible
s
Typical propagation delay: 20 ns
s
Low input current: 1
P
A maximum
s
Low quiescent current: 80
P
A maximum
s
Compatible with bus-oriented systems
s
Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number
MM74HCT373WM
MM74HCT373SJ
MM74HCT373MTC
MM74HCT373N
MM74HCT374WM
MM74HCT374SJ
MM74HCT374MTC
MM74HCT374N
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Descriptions
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS005367
www.fairchildsemi.com
MM74HCT373 • MM74HCT374
Connection Diagrams
Top View
MM74HCT373
Top View
MM74HCT374
Truth Tables
MM74HCT373
Output
Control
L
L
L
H
H
H
L
X
H
L
X
X
LE
Data
373
Output
H
L
Q
0
Z
Output
Control
L
L
L
H
MM74HCT374
Clock
Data
H
L
X
X
Output
(374)
H
L
Q
0
Z
n
n
L
X
H HIGH Level
L LOW Level
Q
0
Level of output before steady-state input conditions were established.
Z High Impedance
H HIGH Level
L LOW Level
X Don’t Care
n
Transition from LOW-to-HIGH
Z High Impedance State
The level of the output before steady state input conditions were
Q
0
established.
www.fairchildsemi.com
2
MM74HCT373 • MM74HCT374
Logic Diagrams
MM74HCT373
MM74HCT374
3
www.fairchildsemi.com
MM74HCT373 • MM74HCT374
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
q
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
)
500
ns
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:

12 mW/
q
C from 65
q
C to 85
q
C.

0.5 to

7.0V

1.5 to V
CC

1.5V

0.5 to V
CC

0.5V
r
20 mA
r
35 mA
r
70 mA

65
q
C to

150
q
C
Max
5.5
V
CC
Units
V
V
4.5
0

40

85
q
C
DC Electrical Characteristics
V
CC
5V
r
10% (unless otherwise specified)
Parameter
Minimum HIGH Level
Input Voltage
V
IL
V
OH
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
V
OL
Maximum LOW Level
Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
I
IN
I
OZ
Maximum Input
Current
Maximum 3-STATE
Output Leakage
Current
I
CC
Maximum Quiescent
Supply Current
V
IN
I
OUT
V
IN
V
CC
or GND
0
P
A
2.4V or 0.5V (Note 4)
8.0
1.0
80
1.3
160
1.5
V
IN
V
OUT
Enable
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
CC
or GND,
V
CC
or GND
V
IH
or VIL
4.5V
5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
4.5V
5.5V
V
CC
4.2
5.7
V
CC

0.1
3.98
4.98
V
CC

0.1
3.84
4.84
V
CC

0.1
3.7
4.7
V
V
V
Conditions
T
A
Typ
2.0
0.8
25
q
C
T
A
Symbol
V
IH

40 to 85
q
C
T
A

55 to 125
q
C
Guaranteed Limits
2.0
0.8
2.0
0.8
Units
V
V
V
IH
or V
IL
r
0.1
r
1.0
r
1.0
P
A
r
0.5
r
5.0
r
10
P
A
P
A
mA
Note 4:
Measured per pin. All others tied to V
CC
or ground.
www.fairchildsemi.com
4
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参数对比
与MM74HCT373MTCX相近的元器件有:MM74HCT373SJ、MM74HCT373N、MM74HCT373MTC、MM74HCT373SJX。描述及对比如下:
型号 MM74HCT373MTCX MM74HCT373SJ MM74HCT373N MM74HCT373MTC MM74HCT373SJX
描述 Networking Modules XPort XE Ext. Temp. without Encryption Latches 3-STATE Oct D-Tp Lat Latches 3-STATE Oct D-Tp Lat Latches 3-STATE Oct D-Tp Lat Latches 3-STATE Oct D-Tp Lat
Brand Name Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor Fairchild Semiconductor
是否无铅 不含铅 不含铅 不含铅 不含铅 不含铅
是否Rohs认证 符合 符合 符合 符合 符合
厂商名称 Fairchild Fairchild Fairchild Fairchild Fairchild
零件包装代码 TSSOP SOP DIP TSSOP SOP
包装说明 TSSOP, TSSOP20,.25 SOP, SOP20,.3 0.300 INCH, PLASTIC, MS-001, DIP-20 TSSOP, TSSOP20,.25 SOP, SOP20,.3
针数 20 20 20 20 20
制造商包装代码 20LD, TSSOP, JEDEC MO-153, 4.4MM WIDE 20LD,SOP,EIAJ TYPE II, 5.3MM WIDE 20LD,MDIP,JEDEC MS-001, .300\" WIDE 20LD, TSSOP, JEDEC MO-153, 4.4MM WIDE 20LD,SOP,EIAJ TYPE II, 5.3MM WIDE
Reach Compliance Code compliant compliant unknown compliant compliant
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99
系列 HCT HCT HCT HCT HCT
JESD-30 代码 R-PDSO-G20 R-PDSO-G20 R-PDIP-T20 R-PDSO-G20 R-PDSO-G20
JESD-609代码 e4 e3 e3 e4 e3
长度 6.5 mm 12.6 mm 26.075 mm 6.5 mm 12.6 mm
负载电容(CL) 50 pF 50 pF 50 pF 50 pF 50 pF
逻辑集成电路类型 BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER BUS DRIVER
最大I(ol) 0.006 A 0.006 A 0.006 A 0.006 A 0.006 A
位数 8 8 8 8 8
功能数量 1 1 1 1 1
端口数量 2 2 2 2 2
端子数量 20 20 20 20 20
最高工作温度 85 °C 85 °C 85 °C 85 °C 85 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
输出极性 TRUE TRUE TRUE TRUE TRUE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP SOP DIP TSSOP SOP
封装等效代码 TSSOP20,.25 SOP20,.3 DIP20,.3 TSSOP20,.25 SOP20,.3
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE IN-LINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
峰值回流温度(摄氏度) 260 260 NOT APPLICABLE 260 260
电源 5 V 5 V 5 V 5 V 5 V
Prop。Delay @ Nom-Sup 37 ns 37 ns 37 ns 37 ns 37 ns
传播延迟(tpd) 56 ns 56 ns 56 ns 56 ns 56 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.2 mm 2.1 mm 5.08 mm 1.2 mm 2.1 mm
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V
表面贴装 YES YES NO YES YES
技术 CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
端子面层 Nickel/Palladium/Gold (Ni/Pd/Au) Matte Tin (Sn) Matte Tin (Sn) Nickel/Palladium/Gold (Ni/Pd/Au) Matte Tin (Sn)
端子形式 GULL WING GULL WING THROUGH-HOLE GULL WING GULL WING
端子节距 0.65 mm 1.27 mm 2.54 mm 0.65 mm 1.27 mm
端子位置 DUAL DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT APPLICABLE NOT SPECIFIED NOT SPECIFIED
宽度 4.4 mm 5.3 mm 7.62 mm 4.4 mm 5.3 mm
湿度敏感等级 1 1 - 1 1
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