NXP Semiconductors
Data Sheet: Advance Information
Document Number: MMPF0200
Rev. 6.0, 8/2016
12 channel configurable power
management integrated circuit
The PF0200 Power Management Integrated Circuit (PMIC) provides a highly
programmable/ configurable architecture, with fully integrated power devices
and minimal external components. With up to four buck converters, one boost
regulator, six linear regulators, RTC supply, and coin-cell charger, the PF0200
can provide power for a complete system, including applications processors,
memory, and system peripherals, in a wide range of applications. With on-chip
One Time Programmable (OTP) memory, the PF0200 is available in pre-
programmed standard versions, or non-programmed to support custom
programming. The PF0200 is especially suited to the i.MX 6SoloLite,
i.MX 6Solo and i.MX 6DualLite versions of the i.MX 6 family of devices and is
supported by full system level reference designs, and pre-programmed
versions of the device. This device is powered by SMARTMOS technology.
Features:
• Three to four buck converters, depending on configuration
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output voltage, sequence, and timing
• OTP (One Time Programmable) memory for device configuration
• Coin cell charger and RTC supply
• DDR termination reference voltage
• Power control logic with processor interface and event detection
• I
2
C control
• Individually programmable ON, OFF, and Standby modes
PF0200
POWER MANAGEMENT
EP SUFFIX (E-TYPE)
56 QFN 8X8
98ASA00405D
ES SUFFIX (WF-TYPE)
56 QFN 8X8
98ASA00589D
Applications
• Tablets
• IPTV
• Industrial Control
• Medical monitoring
• Home automation/ alarm/ energy management
PF0200
VREFDDR
DDR Memory
i.MX6X
DDR MEMORY
INTERFACE
SW3A/B
Processor Core
Voltages
External AMP
Microphones
Speakers
Audio
Codec
SW1A/B
SW2
SWBST
Control Signals
I
2
C Communication
VGEN1
VGEN2
VGEN3
VGEN4
VGEN5
LICELL
Charger
VGEN6
WAM
GPS
MIPI
SD-MMC/
NAND Mem.
SATA
HDD
SATA - FLASH
NAND - NOR
Interfaces
Parallel control/GPIOS
I
2
C Communication
Camera
GPS
MIPI
uPCIe
Sensors
Camera
LDVS Display
HDMI
USB
Ethernet
CAN
COINCELL
Main Supply
Cluster/HUD
Front USB
POD
Rear Seat
Infotaiment
Rear USB
POD
Figure 1. Simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
Table of Contents
1
2
3
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2 PF0200 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8
9
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PF0200
2
NXP Semiconductors
ORDERABLE PARTS
1
Orderable parts
The PF0200 is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device
uses “NP” as the programming code. The pre-programmed devices are identified using the program codes from
Table 1,
which also list
the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in
Table 8.
Contact your NXP representative for more details.
Table 1. Orderable part variations
Part number
MMPF0200NPAEP
MMPF0200F0AEP
MMPF0200F3AEP
MMPF0200F4AEP
MMPF0200F6AEP
MMPF0200F0ANES
MMPF0200F3ANES
MMPF0200F4ANES
Notes
1. For Tape and Reel add an R2 suffix to the part number.
2. For programming details see
Table 8.
-40 to 105 °C
56 QFN 8x8 mm - 0.5 mm pitch
WF-Type QFN (wettable flank)
-40 to 85 °C
56 QFN 8x8 mm - 0.5 mm pitch
E-Type QFN (full lead)
Temperature (T
A
)
Package
Programming
NP
F0
F3
F4
F6
F0
F3
F4
Reference designs
N/A
N/A
N/A
N/A
i.MX6SX-SDB
N/A
N/A
N/A
Extended Industrial
Consumer
Qualification tier
Notes
(2)(1)
(2)(1)
(2)(1)
(2)(1)
(2)(1)
(2)(1)
(2)(1)
(2)(1)
PF0200
NXP Semiconductors
3
INTERNAL BLOCK DIAGRAM
2
Internal block diagram
VIN1
VGEN1
VGEN1
100 mA
PF0200
SW1A/B
Single/Dual
2500 mA
Buck
O/P
Drive
O/P
Drive
SW1FB
SW1AIN
SW1ALX
SW1BLX
SW1BIN
SW1VSSSNS
VGEN2
VGEN2
250 mA
VIN2
VGEN3
VGEN3
100 mA
VGEN4
VGEN4
350 mA
VIN3
VGEN5
Core Control logic
VGEN5
100 mA
SW2
1500 mA
Buck
O/P
Drive
SW2LX
SW2IN
SW2IN
SW2FB
GNDREF1
Initialization State Machine
VGEN6
VGEN6
200 mA
OTP
VDDOTP
Supplies
Control
CONTROL
SW3A/B
Single Phase
2500 mA
Buck
O/P
Drive
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VDDIO
SCL
SDA
I
2
C
Interface
DVS CONTROL
O/P
Drive
DVS Control
VCOREDIG
VCOREREF
VCORE
GNDREF
I
2
C Register
map
Reference
Generation
Trim-In-Package
Clocks and
resets
SWBST
600 mA
Boost
O/P
Drive
SWBSTLX
SWBSTIN
SWBSTFB
VREFDDR
VINREFDDR
Clocks
32 kHz and 16 MHz
VHALF
VIN
Li Cell
Charger
LICELL
Best
of
Supply
VSNVS
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
PWRON
RESETBMCU
ICTEST
Figure 2. PF0200 simplified internal block diagram
PF0200
4
STANDBY
SDWNB
VSNVS
RSVD6
INTB
NXP Semiconductors
PIN CONNECTIONS
3
3.1
Pin connections
Pinout diagram
VCOREREF
VCOREDIG
SWBSTFB
44
SWBSTLX
SWBSTIN
GNDREF
VDDOTP
PWRON
VCORE
56
INTB
SDWNB
RESETBMCU
STANDBY
ICTEST
SW1FB
SW1AIN
SW1ALX
SW1BLX
SW1BIN
RSVD1
RSVD2
RSVD3
SW1VSSSNS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GNDREF1
55
54
53
52
51
50
49
48
47
46
45
VSNVS
43
42
41
40
39
38
37
LICELL
VGEN6
VIN3
VGEN5
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VREFDDR
VINREFDDR
VHALF
36
35
34
33
32
31
30
29
28
VGEN4
VDDIO
SDA
SCL
VIN
21
RSVD6
EP
16
VGEN1
17
VIN1
18
VGEN2
19
RSVD4
20
RSVD5
22
SW2LX
23
SW2IN
24
SW2IN
25
SW2FB
26
VGEN3
27
VIN2
Figure 3. Pinout diagram
PF0200
NXP Semiconductors
5
