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Morph-IC Data Sheet

Version 1.0

Future Technology Devices International Ltd

2004

MORPH-IC Data Sheet Revision 1.0

Introduction

MORPH-IC combines the flexibility of FTDI’s FT2232C USB interface I.C. together with an Altera ACEX

1K series FPGA ( EP1K10TC100-3 ) in a compact ready to use module. The power and IO pins of the

module are brought out onto 2 x 20pin, 0.1in pitch headers on the underside of the pcb, allowing

easy connection to the pins on a 0.1in grid. The module can also be plugged into a pcb using readily

available mating pcb connectors ( two included ). Included on the module are the 3.3V and 2.5V

voltage regulators required by the FPGA as well as a 50MHz CMOS oscillator hard wired to one of its

two clock pins. Power control to meet USB suspend current requirements is provided by the FT2232C

and an on board MOSFET power switch.

MORPH-IC uses the Multi Protocol Synchronous Serial Engine ( MPSSE ) interface of the FT2232C to

program / reprogram the FPGA over USB in a fraction of a second. Not only can the contents of the

FPGA be defined over USB on initialising the application software by loading them from an Altera

format configuration file, but the contents of

the FPGA can be reloaded / redefined “almost”

in real time ( under 0.2 seconds ). This

effectively allows a single product to Morph

between different hardware configurations

under software control ( via USB ) from a

single application.

The second channel of the FT2232C is hard

wired to the IO pins of the FPGA. These can

be used by the FPGA to communicate with the

application software over USB at transfer rates

of up to 1M Byte / second.

These features make MORPH-IC ideal for

instrumentation, communications and other

demanding application areas where flexibility

and in-circuit hardware upgradability are of

paramount importance.

MORPH-IC comes complete with USB drivers for Windows 98/ME/2000/XP, VHDL code examples, FPGA

loader program ( including Delphi source code ) and a Windows DLL interface which can be used to

interface it to most common Windows programming languages. Examples of DLL interfacing in Visual

C++, Visual Basic and Borland Delphi are provided. Linux Drivers and a Linux version of the FPGA

loader written in Kylix are also provided. An example project demonstrating IO over USB is included

complete with VHDL and Delphi source code.

To complete the package, a second CD contaning the Quartus II Software Starter Suite is included.

This contains the free Altera Quartus II Web Edition software which provides a complete environment

for programmable logic device (PLD) design, including schematic- and text-based design entry, HDL

synthesis, place-and-route, verification and simulation. This package runs under Windows NT/2000/XP

and can be used to develop code for the on-board FPGA. Registration with Altera is required in order to

run this package.

MORPH-ICs competitive pricing and quantity discount structure make it ideal for incorporating into

low - medium volume designs. As it comes complete with all FPGA development software required

and example code it is also ideal as a classroom training tool for colleges and universities as well as

engineers wanting to learn more about hardware development using FPGAs.

A range of optional training kits is under development which will allow students / engineers to study

various areas of electronic engineering including A/D and D/A converters, video controllers and TV

interfacing. Training kits consist of an assembled pcb with all the components required for the projects

into which you plug a MORPH-IC module ( extra ). Training kits also come with a CD containing VHDL

code and software source code for the projects in the kit. 3rd party contributions are also welcome - if

you have a MORPH-IC project you would like to share with others please contact us.

MORPH-IC Data Sheet Revision 1.0

Key Features

•

FT2232C Dual USB UART / FIFO I.C.

Altera Acex™ EP1K10TC100-3 FPGA

Ultra fast FPGA configuration / reconfiguration

over USB ( under 0.2 sec )

576 Embedded FPGA Logic Elements

( == 10,000 gates typical )

3 Embedded Logic RAM / ROM Elements

( == 1.5k bytes memory )

FPGA – PC USB Data Transfer at up to 1M

Byte/sec

Onboard 93C56 configuration EEPROM

MOSFET switched 5v and 3.3v power outputs

for powering external logic.

Onboard 6MHz crystal and essential support

components for FT2232C.

Onboard 50MHz oscillator as FPGA primary

clock.

Onboard LEDs indicate USB driver enumeration

and successful FPGA device programming.

•

36 dedicated external IO pins

8 shared external IO pins

4 dedicated external input pins

1 dedicated external clock input

Powered from USB bus or external PSU

Standard 0.1in pitch format connector pins,

ideal for rapid prototyping and small-medium

size production runs.

FTDI’s VCP and D2XX USB Windows and Linux

USB drivers ( provided ) eliminate the need

for driver development in most cases.

Windows FPGA loader interface DLL supplied

including interface examples in VB, VC++ and

Delphi.

Stand-alone FPGA loader programs provided

for Windows and Linux.

VHDL programming examples ( I/O over USB )

provided.

Delphi application software examples including

source code provided.

MORPH-IC schematics provided.

Free Altera Quartus II Web Edition

development software included.

FIGURE 1 - MORPH-IC BLOCK DIAGRAM ( simplified )

VCC(USB)

MOSFET POWER SWITCH

VCC(5V)

3.3V

REGULATOR

2.5V

REGULATOR

VCC(3.3V)

CN1

USB

CONNECTOR

PROGRAMMING

INTERFACE

VCORE

IO CONNECTORS

FT2232C

USB INTERFACE

I.C.

DATA TRANSFER

INTERFACE

GND

6MHz XTAL /

RESONATOR

ALTERA ACEX

EP1K10TC-100

FPGA

INT CLOCK

( PIN 90 )

EXT CLOCK

( PIN 39 )

93C56 USB

CONFIGURATION

EEPROM

50MHz

OSCILLATOR

J2-14

MORPH-IC Data Sheet Revision 1.0

FIGURE 2 - MORPH-IC KEY COMPONENT LOCATION

Figure 2 ( left ) shows the location of the key

components on the MORPH-IC module viewed

from above. The module is connected to USB

by plugging a USB “A” to “B” cable ( available

separately ) into the USB type “B” connector

shown at the top. Fitting a jumper on JP1 selects

USB Bus Powered Mode ( the default ) where

the module obtains its power from USB. To

change the module to USB self powered mode,

remove the jumper on JP1 and supply +5v

from an external PSU to J1 pin 1. The 93C56

EEPROM is pre-programmed at the factory with

the correct defaults for MORPH-IC operation. If

re-programming this using FTDI’s MPROG utility,

great care must be taken or the module and its

utilities may cease to work.

Two voltage regulators are provided on the

module - the 2.5V regulator provides the

power to the FPGA core logic, whilst the 3.3V

regulator provides power to the FPGA IO cells.

The output of the 3.3V regulator is available

through dedicated pins on J1 and J2 to supply up

to 250mA of current to external logic. The 3.3v

supply is switched off during USB suspend to

conserve current.

A 50Mhz oscillator is provided on the module and

is hard wired to clock pin 90 of the EP1K10TC-

100 FPGA. For applications requiring a different

clock frequency, use clock pin 39 of the FPGA

which is connected to J2 pin 14. A full listing of

the pinouts of J1 and J2 is provided in Figure 5.

A 6MHz resonator on the module provides the master clock for the FT2232C. For detailed descriptions

of the FT2232C and EP1K10TC-100, please consult the relevant data sheets. The FT22232C data sheet

and application note can be found on the enclosed CD. The EP1K10TC-100 data sheet can be found on

the Altera web site at http://www.altera.com/literature/lit-acx.jsp

FIGURE 3 - MORPH-IC FPGA PROGRAMMING INTERFACE

MPSSE INTERFACE

TCK

TDI

TDO

TMS

GPIOL0

GPIOL3

DCLK

DATA0

NCONFI

NSTATUS

CONF_DONE

DATA3

FT2232C

USB INTERFACE

I.C.

ALTERA ACEX 1K

EP1K10TC-100

FPGA

MORPH-IC FPGA PROGRAMMING INTERFACE

MORPH-IC Data Sheet Revision 1.0

Figure 3 shows the programming interface between the FT2232C and the EP1K10TC-100. It uses the

multi-protocol synchronous serial engine feature ( MPSSE ) of the FT2232C channel A to program the

FPGA “on-the-fly”. The FPGA can be programmed / reprogrammed in under 0.2 seconds which makes

it possible to design some type of products that would not normally fit into this size of FPGA by using

several different configuration files for different modes of operation and loading / re-loading these

transparently to the end-user. The configuration files are output from the Altera Quartus ™ software

and can be downloaded into the FPGA either manually by using the loader program supplied or under

application software control by using the DLL supplied.

For further details of MPSSE operation, consult the FT2232C data sheet and the application note

AN2232C-01 downloadable from FTDI’s web site at page http://www.ftdichip.com/FT2232C2.htm. The

source code for the loader program and the DLL illustrate how to program the MPSSE as an Altera

ACEX series loader. MORPH-IC uses the GPIOL0 pin of the FT2232C to detect / verify the completion of

FPGA device configuration and the GPIOL3 pin of the FT2232C to provide a reset to the FPGA via pin

79.

FIGURE 4 - MORPH-IC FPGA DATA TRANSFER INTERFACE

FIFO INTERFACE

BD0

BD1

BD2

BD3

BD4

BD5

BD6

BD7

RXF#

TXE#

RD#

SI/WUB

FT2232C

USB INTERFACE

I.C.

ALTERA ACEX

EP1K10-100

FPGA

Figure 4 shows the bi-directional data transfer interface between the FT2232C and the EP1K10TC-100.

MORPH-IC FPGA DATA

allow the FPGA to communicate

It uses the FIFO mode of the FT2232C channel B to

TRANSFER INTERFACE

with a PC over

USB. Data is read / written between the devices over an 8 bit data bus BD0 .. BD7.

A typical application would send “commands” to the FPGA which would be interpreted by a state

machine inside the FPGA. Some commands may return data from the FPGA to the application.

To send data to the application poll TXE# until it is low then place the data to be transmitted on BD0 ..

BD7. Enable the bus, strobe the WR pin high then low then disable ( tri-state ) the data bus pins. Data

is written into the FT2232C on the falling edge of WR.

To receive commands / data from the application, poll RXF# until it is low which means that there is

data in the FT2232C to be read. Take RD# low to enable the data from the FT2232C on BD0 .. BD7.

Strobe the data into the FPGA and make RD# high ( its default state ) to tri-state the bus.

For further details of the FT2232C FIFO mode including timings please consult the FT2232C data sheet.

The example project on the CD illustrates such an application. Full VHDL source code of the project and

the Delphi 5 application program are pubished on the CD and are a good starting point for developing

MORPH-IC projects.

Note : The data bus and interface pins are all brought out on the J1 / J2 IO connectors. The data bus

can be used to send / receive data to other external devices when the FT2232C interface is in its idle

state.

MORPH-IC Data Sheet Revision 1.0