Freescale Semiconductor, Inc.
Order Number: MPC750EC/D
Rev. 2.3, 9/2001
Semiconductor Products Sector
Freescale Semiconductor, Inc...
S
E
Technical Data
AL
MPC750A RISC Microprocessor
SC
EE
Hardware Specifications
FR
BY
This document is primarily concerned with the MPC750, however, unless otherwise noted, all information
ED
IV
here applies also to the MPC740. The MPC750 and MPC740 are implementations of the PowerPC™
CH
family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent
AR
physical characteristics of the MPC750. For functional characteristics of the processor, refer to the
MPC750 RISC Microprocessor User’s Manual
.
The MPC750 (and MPC740) is implemented in several semiconductor fabrication processes. Different
processes may require different supply voltages and may have other electrical differences but will have the
same functionality. As a designator to distinguish between MPC750 implementations in various processes,
a suffix is added to the MPC750 part number as shown below:
Table 1. MPC750 Microprocessors from Motorola
Part Number
MPC750A, MPC740A
XPC750P, XPC740P
Process
0.29 µ
m
CMOS, 5LM
0.25 µ
m
CMOS, 5LM
Core
Voltage
2.6 V
1.9 V
I/O
Voltage
3.3 V
3.3 V
5-Volt
Tolerant
No
No
CO
I
M
E
,I
OR
CT
DU
N
C.
N
This document will describe only the MPC750A implementation. The XPC750P is described in a separate
document.
This document contains information on a new product under development by Motorola.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc., 2001. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
This document contains the following topics:
Topic
Page
Freescale Semiconductor, Inc...
ED
updates for this document, refer to the website at
To locate any published errata or
IV
http://www.mot.com/PowerPC/.
CH
AR
Section 1.1, “Overview”
Section 1.2, “Features”
Section 1.3, “General Parameters”
Section 1.4, “Electrical and Thermal Characteristics”
Section 1.4.1, “DC Electrical Characteristics”
Section 1.4.2, “AC Electrical Characteristics”
Section 1.4.2.1, “Clock AC Specifications”
Section 1.4.2.2, “60x Bus Input AC Specifications”
Section 1.4.2.3, “60x Bus Output AC Specifications”
Section 1.4.2.4, “L2 Clock AC Specifications”
Section 1.4.2.5, “L2 Bus Input AC Specifications”
Section 1.4.2.6, “L2 Bus Output AC Specifications”
Section 1.5, “Pin Assignments”
LE
Section 1.6, “Pinout Listings”
CA
Section 1.7, “Package Description”
ES
RE
Section 1.8, “System Design Information”
F
Y
Section 1.9, “Document Revision History
B
S
CO
I
M
E
R,
TO
UC
ND
3
4
6
6
6
10
C.
10
IN
12
14
15
18
19
23
25
29
31
42
2
MPC750A RISC Microprocessor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Overview
1.1 Overview
The MPC750 is targeted for low-cost, low-power systems and supports the following power management
features—doze, nap, sleep, and dynamic power management. The MPC750 consists of a processor core
and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus.
Figure 1 shows a block diagram of the MPC750.
Control Unit
Instruction Fetch
Branch Unit
Completion
Freescale Semiconductor, Inc...
System Unit
Dispatch
FXU1
FXU2
CH
AR
ED
IV
BY
EE
FR
LE
CA
S
S
CO
I
M
E
,I
OR
32K ICache
CT
U
ND
C.
N
BHT/BTIC
GPRs
LSU
FPRs
Rename
Buffers
FPU
Rename
Buffers
L2 Cache
32K DCache
L2 Tags
BIU
60x BIU
Figure 1. MPC750 Block Diagram
MPC750A RISC Microprocessor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
3
Freescale Semiconductor, Inc.
Features
1.2 Features
This section summarizes features of the MPC750’s implementation of the PowerPC architecture. Major
features of the MPC750 are as follows:
•
Branch processing unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resolving 2 speculations)
— Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
C.
N
— 64-entry, 4-way set associative branch target instruction cache (BTIC) for
I
eliminating branch
,
delay slots
OR
Dispatch unit
CT
U
— Full hardware detection of dependencies (resolved in the
ND
execution units)
— Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit
CO
I
M
1, fixed-point unit 2, or floating-point)
SE
— Serialization control (predispatch, postdispatch, execution serialization)
LE
Decode
CA
ES
— Register file access
RE
— Forwarding control
F
Y
B
— Partial instruction decode
D
E
Load/store unit
IV
— One cycle
CH
or store cache access (byte, half-word, word, double-word)
load
AR
— Effective address generation
— Hits under misses (one outstanding miss)
— Single-cycle misaligned access within double word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian support in hardware
Fixed-point units
— Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
— Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shift, rotate, logical
— Multiply and divide support (multi-cycle)
— Early out multiply
Floating-point unit
— Support for IEEE-754 standard single- and double-precision floating-point arithmetic
— 3 cycle latency, 1 cycle throughput, single-precision multiply-add
•
Freescale Semiconductor, Inc...
•
•
•
•
4
MPC750A RISC Microprocessor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Features
•
•
•
•
•
•
— 3 cycle latency, 1 cycle throughput, double-precision add
— 4 cycle latency, 2 cycle throughput, double-precision multiply-add
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode
System unit
— Executes CR logical instructions and miscellaneous system instructions
— Special register transfer instructions
C.
Cache structure
N
,I
— 32K, 32-byte line, 8-way set associative instruction cache
OR
— 32K, 32-byte line, 8-way set associative data cache
CT
— Single-cycle cache access
DU
ON
— Pseudo-LRU replacement
IC
— Copy-back or write-through data cache (on a page per page basis)
M
SE
— Supports all PowerPC memory coherency modes
LE
outstanding miss under hits)
— Non-blocking instruction and data cache (one
CA
— No snooping of instruction cache
ES
RE
Memory management unit
F
Y
— 128 entry, 2-way set associative instruction TLB
B
D
associative data TLB
E
— 128 entry, 2-way set
IV
— Hardware
CH
for TLBs
reload
— 4 instruction BATs and 4 data BATs
AR
— Virtual memory support for up to 4 exabytes (2
52
) of virtual memory
— Real memory support for up to 4 gigabytes (2
32
) of physical memory
Level 2 (L2) cache interface (not implemented on MPC740)
— Internal L2 cache controller and 4K-entry tags; external data SRAMs
— 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support
— Copy-back or write-through data cache (on a page basis, or for all L2)
— 64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size
— Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous
burst SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported
Bus interface
— Compatible with 60x processor interface
— 32-bit address bus
— 64-bit data bus
— Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x
supported
Integrated power management
— Low-power 2.6/3.3-volt design
— Three static power saving modes: doze, nap, and sleep
Freescale Semiconductor, Inc...
MPC750A RISC Microprocessor Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
5
