Freescale Semiconductor
Technical Data
MPC8541EEC
Rev. 4, 12/2006
MPC8541E PowerQUICC™ III
Integrated Communications Processor
Hardware Specifications
The MPC8541E integrates a PowerPC™ processor core
built on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8541E is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the
MPC8555E
PowerQUICC™ III Integrated Communications Processor
Reference Manual.
To locate any published errata or updates for this document
refer to http://www.freescale.com or contact your Freescale
sales office.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ethernet: Three-Speed, MII Management . . . . . . . . . . 20
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 53
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
System Design Information . . . . . . . . . . . . . . . . . . . . . 75
Document Revision History . . . . . . . . . . . . . . . . . . . . 82
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 82
© Freescale Semiconductor, Inc., 2004, 2004, 2006. All rights reserved.
Overview
1
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Overview
The following section provides a high-level overview of the MPC8541E features.
Figure 1
shows the
major functional units within the MPC8541E.
DDR
SDRAM
DDR SDRAM Controller
I
2
C Controller
DUART
GPIO
32b
IRQs
Local Bus Controller
Programmable
Interrupt Controller
CPM
FCC
FCC
Serial
DMA
Security
Engine
256 Kbyte
L2 Cache/
SRAM
e500 Core
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
e500
Coherency
Module
Core Complex
Bus
64/32b PCI Controller
OCeaN
0/32b PCI Controller
DMA Controller
ROM
I-Memory
Serial Interfaces
MIIs/RMIIs
DPRAM
RISC
Engine
Parallel I/O
Baud Rate
Generators
Timers
CPM
Interrupt
Controller
SPI
I2C
10/100/1000 MAC
10/100/1000 MAC
I/Os
MII, GMII, TBI,
RTBI, RGMIIs
Figure 1. MPC8541E Block Diagram
1.1
Key Features
The following lists an overview of the MPC8541E feature set.
• Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Overview
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Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels, a Controller,
and a set of crypto Execution Units (EUs). The Execution Units are:
— Public Key Execution Unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511-bits
— Data Encryption Standard Execution Unit (DEU)
– DES, 3DES
– Two key (K1, K2) or Three Key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced Encryption Standard Unit (AESU)
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and Counter modes
— ARC Four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message Digest Execution Unit (MDEU)
– SHA with 160-bit or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random Number Generator (RNG)
— 4 Crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
High-performance RISC CPM
— Two full-duplex fast communications controllers (FCCs) that support the following protocol:
– IEEE802.3/Fast Ethernet (10/100)
— Serial peripheral interface (SPI) support for master or slave
— I
2
C bus controller
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
256 Kbytes of on-chip memory
— Can act as a 256-Kbyte level-2 cache
— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays
— Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
— Full ECC support on 64-bit boundary in both cache and SRAM modes
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Overview
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— SRAM operation supports relocation and is byte-accessible
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing)
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines
– Individual line locks set and cleared through Book E instructions or by externally mastered
transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI
– Four inbound windows
– Four outbound windows plus default translation for PCI
DDR memory controller
— Programmable timing supporting first generation DDR SDRAM
— 64-bit data interface, up to MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Sleep mode support for self refresh DDR SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
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Overview
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— Four global high resolution timers/counters that can generate interrupts
— Supports additional internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
Two I
2
C controllers (one is contained within the CPM, the other is a stand-alone controller which
is not part of the CPM)
— Two-wire interface
— Multiple master support
— Master or slave I
2
C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the stand-alone I
2
C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I
2
C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (RXD, TXD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Two Three-speed (10/100/1000)Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers
— Support for Ethernet physical interfaces:
– 10/100/1000 Mbps IEEE 802.3 GMII
– 10/100 Mbps IEEE 802.3 MII
– 10 Mbps IEEE 802.3 MII
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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